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Message
From: xcsnake at free.fr<xcsnake@f...>
Date: Wed Mar 21 16:32:09 CET 2007
Subject: [oc] memory controller and Cke for SDRAM
Hello,
I'm working with the memory controller IP core to use a SDRAM from Rudolf
Usselmann and have a little problem with the Cke signal.
I have posted an image on my website to show the problem :
http://xcsnake.free.fr/sdram_cke.png
In my case, the write (we+cas+cs) signal is not taken by the SDRAM. This is
because inside the RAM, the cke is late of 1 clock cycle (the
signal without a name is the internal SDRAM clock signal). To correct this,
the memory controller cke signal should be one clock cycle before. Is it a bug,
or did I do something wrong ?
Thank you
Mickaël
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