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    Navigation: All forums > Cores > Message List > Message Post

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    From: Thilo Jeremias<jeremias@o...>
    Date: Sat Mar 10 00:42:37 CET 2007
    Subject: [oc] Serial / UART link to host
    Top
    most of the uarts on opencores come with tons of features hat you love
    if you got a cpu connected,
    if you just need a single baud-rate no fifo features no handshakes (or
    only cts/dts) you are better of looking at
    something as simple as http://direct.xilinx.com/bvdocs/appnotes/xapp341.pdf
    that gets communication up and running in a couple of hours.

    thilo


    Guy Hutchison wrote:
    > This BSD page has some good information on the standard UART register
    > set. In general your FPGA will need to have either a small
    > microprocessor or a state machine to program the initial parameters
    > into the UART and then push data into and out of it.
    >
    > Link:
    > http://www.freebsd.org/doc/en_US.ISO8859-1/articles/serial-uart/article.html
    >
    > - Guy
    >
    > On 3/9/07, *manuel.kampert@o...
    > <mailto:manuel.kampert@o...>* <manuel.kampert@o...
    > <mailto:manuel.kampert@o...>> wrote:
    >
    > The core that i've used was
    >
    > http://www.opencores.org/pdownloads.cgi/list/a_vhd_16550_uart
    >
    > Unfortunately it did not contain any testbench.
    >
    >
    >
    > ----- Original Message -----
    > From: Günter Dannoritzer<dannoritzer@w...>
    > To:
    > Date: Fri Mar 9 14:00:39 CET 2007
    > Subject: [oc] Serial / UART link to host
    >
    > > manuel.kampert at online.de <http://online.de> wrote:
    > > > Hello!
    > > [...]
    > > > I choosed the VHDL USART circuit from this forum and read the
    > > > documentation. I was quite impressed about the complexity of
    > > this
    > > > module and was unable to figure out how to just send some
    > > single bytes
    > > > to my machine.
    > > >
    > > Maybe I overlooked one, but do you mean the
    > > Serial UART
    > > http://www.opencores.org/projects.cgi/web/uart
    > <http://www.opencores.org/projects.cgi/web/uart>
    > > or the
    > > UART 16550
    > > http://www.opencores.org/projects.cgi/web/uart16550
    > > The first one has a VHDL testbench, the later one only a Verilog
    > > one. If
    > > there is nothing in the documentation, the test bench might be the
    > > best
    > > place to look how they feed data into the core.
    > > Cheers,
    > > Guenter
    > > > Does someone have some lines of code that would give me a
    > > start to
    > > > initialize this circuit?
    > > >
    > > > Many Thanks,
    > > > Manue.
    > > > _______________________________________________
    > > > http://www.opencores.org/mailman/listinfo/cores
    > > >
    > >
    > >
    > _______________________________________________
    > http://www.opencores.org/mailman/listinfo/cores
    > <http://www.opencores.org/mailman/listinfo/cores>
    >
    >
    > ------------------------------------------------------------------------
    >
    > _______________________________________________
    > http://www.opencores.org/mailman/listinfo/cores


    ReferenceAuthor
    [oc] Serial / UART link to hostGuy Hutchison

     
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