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From: Günter Dannoritzer<dannoritzer@w...>
Date: Fri Mar 9 14:00:39 CET 2007
Subject: [oc] Serial / UART link to host
manuel.kampert@o... wrote:
> Hello!
[...]
> I choosed the VHDL USART circuit from this forum and read the
> documentation. I was quite impressed about the complexity of this
> module and was unable to figure out how to just send some single bytes
> to my machine.
>

Maybe I overlooked one, but do you mean the

Serial UART
http://www.opencores.org/projects.cgi/web/uart

or the

UART 16550
http://www.opencores.org/projects.cgi/web/uart16550

The first one has a VHDL testbench, the later one only a Verilog one. If
there is nothing in the documentation, the test bench might be the best
place to look how they feed data into the core.

Cheers,

Guenter



> Does someone have some lines of code that would give me a start to
> initialize this circuit?
>
> Many Thanks,
> Manue.
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> http://www.opencores.org/mailman/listinfo/cores
>

Reference	Author
[oc] Serial / UART link to host	Manuel kampert