OPENCORES.ORG

Thank you very much for the help we greatly appreciate you taking the

In tri mode core, data path become 32-bit at very end of data path
near User interface FIFO,
If you want to enjoy low power (at expense of Area) then just after
GMII start 32-bit operations...

On 2/13/07, EPetrichenko@g... <EPetrichenko@g...> wrote:
> Thank you very much for the help we greatly appreciate you taking the
> time and sending us all that information.
>
> Also the 8 bit MAC was only used for explanation purposes in our
> documents; we will be using the opencores tri mode Ethernet which has
> 32 bit MAC in the actual project.  It will also be full duplex.  For
> the actual project we will be using the XUP2VPro board.
>
> ALSO DOES ANYONE HAVE A SATA IMPLEMENTATION THAT RECEIVES AS WELL AS
> SENDS SATA DATA FRAMES? THAT WOULD BE A HUGE HELP IF ANYONE HAD
> ANYTHING THAT THEY COULD OFFER US.... THANK YOU VERY MUCH.
>
> Eric
>
> ----- Original Message -----
> From: Umair Siddiqui<umairsiddiqui84@g...>
> To:
> Date: Mon Feb 12 07:49:04 CET 2007
> Subject: [oc] SATA to Ethernet
>
> > sorry I forgot to mention MDIO...
> >
> > On 2/12/07, Umair Siddiqui <umairsiddiqui84 at gmail.com>
> > wrote:
> > > well, as far a 1000 Mb/s MAC design is concerned, it is
> > cheaper and
> > > easier to implement it in FPGA. More over since you are need
> > only
> > > 1000 Mbps Full duplex, MAC is essentially reduced, no half
> > duplex
> > > collision detection.
> > >
> > > just grab the standard from
> > > http://standards.ieee.org/getieee802/802.3.html
> > >
> > > read section 1 (chapter 2, 3, 4 ) --- general mac operation
> > > read section 2 (annex 31a, 31b) --- pause frame handling and
> > flow
> > > control in full duplex
> > > read section 3 (chapter 35) --- GMII interface.
> > >
> > > required features:
> > > - GMII interface: keep the design around GMII, if you need
> > RGMII or
> > > SGMII then add it as extender (for RGMII extender is available
> > from
> > > Xilinx: http://direct.xilinx.com/bvdocs/appnotes/xapp692.pdf)
> > >
> > > - if 125 MHz clock (GMII speed) is ok then go ahead make a
> > 8-bit data
> > > path. otherwise make it wider (bit tough...but manageable ;-)
> > ). For
> > > CRC calculation in wider path, see
> > > www.da.isy.liu.se/pubs/tomhe/ASPDAC2003_crc.pdf (fig 3, pg2).
> > > individual crc function can be generated from
> > > (http://www.easics.com/webtools/crctool).
> > >
> > > - on clientside implement a fifo based interface is easier to
> > > integrate (see tri mode ethernet core) with hardware. but your
> > case
> > > could be different -- cann't comment on system level issues
> > (see
> > > 10/100 MAC core for DMA/Buffer descriptor style).
> > >
> > > - pause frame handling is a must, automatic pause frame
> > generation (in
> > > case of RX user interface FIFO nearly full operation) and flow
> > > control.
> > >
> > > so look at docs and existing opensource code -- and then go
> > for clean
> > > room implementation to save LUTs...good luck
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > > On 2/12/07, EPetrichenko at gmail.com <EPetrichenko at
> > gmail.com> wrote:
> > > > Hello Everyone,
> > > >
> > > > Thank you for the responses, we really appreciate it. My
> > senior design
> > > > team has taken a look at the Wikipedia link posted and it
> > looks like what
> > > > we are trying to do is very similar to what we read.
> > However, we are
> > > > not concerned with the total implementation, what we are
> > concerned
> > > > with is the bridge from SATA to Ethernet. Perhaps this
> > bridge will be
> > > > used in implementing the ATA over Ethernet. The scope of
> > our project
> > > > basically ranges from accepting the MAC packets from the
> > Ethernet and
> > > > passing it along to an FPGA board using the SATA port. To
> > implement
> > > > our project we are planning on using the 1Gb/s opencores
> > version of the
> > > > MAC. Sadly we have not yet begun the implementation of
> > the project.
> > > > If you need more information please go to our website and
> > look under
> > > > the Final Report page:
> > > > www.engr.uconn.edu/ece/SeniorDesign/projects/ecesd84
> > > >
> > > > Thank you.
> > > >
> > > > If anyone has any code that can be used to implement this
> > project and
> > > > is willing to discuss or provide this information it
> > would be of much use
> > > > to us and greatly appreciated. Once again, thank you.
> > > >
> > > > Eric
> > > >
> > > > ----- Original Message -----
> > > > From: Macakolo<yky2820 at y...>
> > > > To:
> > > > Date: Wed Feb 7 05:54:40 CET 2007
> > > > Subject: [oc] SATA to Ethernet
> > > >
> > > > > Hail,
> > > > >
> > > > > This sounds just the type of solution that I had
> > been searching
> > > > > around
> > > > > for months. I am working on a FPGA solution which
> > process data and
> > > > > want to output ALL data onto a HD but no interface
> > right now.
> > > > > If we could have data go through the AOE onto the
> > HDD, which shall
> > > > > be
> > > > > the simlest way to do!!
> > > > > You have any update on your side of this work??
> > > > > Thanks,
> > > > > ----- Original Message -----
> > > > > From: kabbey at biomaps.rutgers.edu<kabbey at
> > b...>
> > > > > To:
> > > > > Date: Tue Feb 6 02:44:24 CET 2007
> > > > > Subject: [oc] SATA to Ethernet
> > > > > > Hi,
> > > > > >
> > > > > > I am interested to use this for a clustered
> > file system. I > > > found a > > > > good
> > starting point on wikipedia: > > > >
> > http://en.wikipedia.org/wiki/Ata_over_ethernet > > > >
> > How is this different from what you would like to do? > >
> > > > Thanks, > > > > Kevin > > > >
> > ----- Original Message ----- > > > > From: H. Peter
> > Anvin<hpa at z...> > > > > To: > > >
> > > Date: Mon Feb 5 15:56:27 CET 2007 > > > > Subject:
> > [oc] SATA to Ethernet > > > > > epetrichenko at
> > gmail.com wrote: > > > > > > My senior design
> > group and I are working on a what > > > we > > >
> > > call a > > > > > "Gigabit > > >
> > > > > Ethernet Board", the goal is to extract data
> > > > > from > > > > the FIS > > > >
> > > of the SATA > > > > > > data frame and send
> > it to the Ethernet. This > > > objective > > >
> > > would > > > > > have to be > > > >
> > > > bidirectional [SATA<->Ethernet]. We are using >
> > > > the > > > > MAC > > > > > code
> > found on > > > > > > opencores to implement the
> > gigabit MAC. The > > > information > > > > in
> > the > > > > > FIS of > > > > > >
> > the SATA data frame will be MAC data packets. > > > >
> > > > > > > > > > If anybody has any advice
> > on how to achieve the > > > objective > > > >
> > or > > > > > vhdl > > > > > > code
> > that can be reused for our purposes, please > > > feel
> > > > > > free to > > > > > contact >
> > > > > > > us. > > > > > Are you
> > implementing a bridge from SATA to > > >
> > ATA-over-Ethernet? > > > > If > > > > >
> > so, it > > > > > will likely be very useful to a lot
> > of people. > > > > > -hpa > > > > >
> > > > > > > > > > > > > > >
> > > > > > > > > >
> > _______________________________________________ > >
> > http://www.opencores.org/mailman/listinfo/cores > > >
> >
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