OPENCORES.ORG

I recently ripped the ddrsdram controller out of EDK

Please i'm looking for a working DDR SDRAM controller; i want to
control a dual ranked ddr sdram 64Mx64; i don't know how to configure
the opencore controller to get it working. can you help me?

----- Original Message ----- 
From: Tom at slim.opencores.org<Tom@s...> 
To: 
Date: Thu Jan 19 03:26:44 CET 2006 
Subject: [oc] DDR SDRAM controller 

> I recently ripped the ddrsdram controller out of EDK 
> (opbddr_v2_00_b) 
> and got it working. There are a few bugs but they are things I can 
> live with as I intend to use it as a piece of stand-alone IP where 
> I 
> have explicit control of the interface. This version supports 
> bursts 
> of 8. If you are still interested in doing this, send me an email 
> describing the problems you have & I'll try to give you a few 
> tips. 
> ----- Original Message ----- 
> From: Mike Delaney<mmdst23 at g...> 
> To: 
> Date: Sat Dec 17 02:18:22 CET 2005 
> Subject: [oc] DDR SDRAM controller 
> > I tried it about a year ago, and never did get it to work. 
> IIRC it 
> > didn't support burst read/writes at the time either, but that 
> may 
> > have 
> > changed. I ended up trying to rip out the controller from the 
> EDK 
> > core and wrote an OPB wrapper to talk to it, but that also 
> didn't 
> > work 
> > on hardware. (This was for a school project, so we gave up on 
> DDR 
> > at 
> > the end of the semester). 
> > I hope you have much better luck then I did. 
> > Mike 
> > On 12/13/05, jihoon at margi.com <jihoon at margi.com> 
> wrote: 
> > > I did the same thing you are trying to do. 
> > > But I think it's too late. 
> > > If you have any question, send me an email. 
> > > 
> > > /Jihoon 
> > > 
> > > ----- Original Message ----- 
> > > From: Anna D. Ashley<ada at c...> 
> > > To: 
> > > Date: Mon Aug 29 17:19:33 CEST 2005 
> > > Subject: [oc] DDR SDRAM controller 
> > > 
> > > > Hi all, 
> > > > 
> > > > meanwhile I had some questions from some of you 
> about my 
> > problem 
> > > > and 
> > > > solutions. Unfortunately I have not solved this 
> problem 
> > and it 
> > > > seems to 
> > > > be no solution. MIG007 works with a couple of test 
> boards 
> > supported 
> > > > by 
> > > > Xilinx and does not work with the rest (or I could 
> not 
> > find out how 
> > > > to 
> > > > bring it to work). So I switched to the open cores 
> DDR 
> > SDRAM 
> > > > controller 
> > > > design but it is going not so fast because there is 
> no 
> > any 
> > > > help\documentation\support. 
> > > > If someone would solve the problem just let me know. 
> > > > Also if someone has already used open cores 
> controller 
> > please tell 
> > > > me. 
> > > > Best, 
> > > > Anna 
> > > > xjf77 at opencores.org wrote: 
> > > > >Hi, Anna, 
> > > > > I am also working on DDR SDRAM Controller. 
> Would you 
> > please 
> > > > tell me 
> > > > >if you have solved this problem? If yes, which 
> tool 
> > did you 
> > > > use? MIG007 
> > > > >or open core from here? 
> > > > > Cheers, 
> > > > >xjf77 
> > > > > 
> > > > >----- Original Message ----- 
> > > > >From: ada at cwazy.co.uk<ada at c...> 
> > > > >To: 
> > > > >Date: Wed Aug 10 12:06:43 CEST 2005 
> > > > >Subject: [oc] DDR SDRAM controller 
> > > > > 
> > > > > 
> > > > > 
> > > > 
> > > > 
> > > _______________________________________________ 
> > > http://www.opencores.org/mailman/listinfo/cores 
> > > 
> > 
> > 
> 
> 