|
Message
From: John Sheahan<jrsheahan@o...>
Date: Thu Feb 8 10:34:59 CET 2007
Subject: [oc] verilog to vhdl converter
gandesiri@g... wrote:
> John,
>
> Can you send me the tool to convert verilog code to vhdl?
>
http://www.taudelta.com.au/v2vhd.html
> Thanks
> Venu
>
> ----- Original Message -----
> From: John Sheahan <jrsheahan@o...>
> To: cores@o...
> Date: Fri, 4 Apr 2003 20:15:31 +1000
> Subject: [oc] verilog to vhdl converter
>
>>
>> Hi
>>
>> I recently wrote a perl script for converting synthesizeable
>> verilog to vhdl.
>>
>> It copes with most of the structures I use, but is bound to
>> suffer when other styles are involved.
>>
>> Is there any interst is posting and assisting tweaking this?
>> I'd like fragments of code it has trouble with, and the expected
>> result (both if it works, and does not, for regression)
>>
>> john
>>
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores
|
 |
Browse
