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Message
From: Richard Herveille<richard@h...>
Date: Mon Jan 29 17:48:42 CET 2007
Subject: [oc] Wishbone interface
ALL wishbone signals are registered on the rising edge of CLK_I.
However Wishbone Classic allows ACK_O to be generated as
ACK_O = CYC_I & STB_I
This allows single cycle transfers.
Richard
-----Original Message-----
From: cores-bounces@o... [mailto:cores-bounces@o...] On
Behalf Of jimyiigor@y...
Sent: Monday, January 29, 2007 6:04 PM
To: cores@o...
Subject: [oc] Wishbone interface
Hello, I'm from Serbia and I am doing a VLSI project for school and my
collegues and I can't figure something out. Question is about rule 4.10:
The clock input [CLK_I] to each IP core MUST coordinate all activities
for the internal logic within the WISHBONE interface. All WISHBONE
output signals are registered at the rising edge of [CLK_I]. All WISHBONE
input signals must be stable before the rising edge of [CLK_I].
We can't agree on word 'registered'. For example some of as says that
ACK_O signal of a slave can be set on falling edge of CLK_I so that
master can detect it on next rising edge. But does this sentence : "All
WISHBONE output signals are registered at the rising edge of [CLK_I]"
means that we can only set ACK_O on rising edge of CLK_I or it means
something else?
We really need an experts opinion on this. Thank you.
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