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Message
From: edb6628 at hotmail.com<edb6628@h...>
Date: Sat Jan 20 01:45:25 CET 2007
Subject: [oc] Implementing Ethernet PHY in Verilog
----- Original Message -----
From: Mikhail Matusov<misoma@r...>
To:
Date: Fri Jan 19 22:24:43 CET 2007
Subject: [oc] Implementing Ethernet PHY in Verilog
> On Fri, 19 Jan 2007 13:10:08 -0800
> "Guy Hutchison" <ghutchis at gmail.com> wrote:
> > This one has me scratching my head. How do you connect an MII
> MAC to an
> > RMII MAC? MII has 4 SDR data pins per direction, while RMII
> has 2 DDR pins
> > per direction.
> >
> Xilinx has an appnote on how to convert GMII to RGMII. Basically
> you
> just need a layer of external DDR registers with some simple logic.
> So,
> I guess when the OP said the parts are connected back-to-back he
> omitted
> this little detail. Personally I think adding a PHY layer in this
> application would be a HUGE overkill.
> /Mikhail
>
>
True, my apologies. It is currently configured as MII to MII. Newer
revisions of the BME revealed that the interface on the BME has
changed from MII to RMII. Implementing a 100Mb PHY is not a trivial
task, this is why I was asking. I have seen an article at Comms Design:
http://www.commsdesign.com/showArticle.jhtml;jsessionid=FAG3F3AMSLDPQQSNDLQCKHSCJUNN2JVN?articleID=192200605
as a place to start but again it is MII to MII.
-E
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