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From: edb6628 at hotmail.com<edb6628@h...>
Date: Sat Jan 20 01:34:48 CET 2007
Subject: [oc] Implementing Ethernet PHY in Verilog
True, my apologies. It is currently configured as MII to MII. Newer
revisions of the BME revealed that the interface on the BME has
changed from MII to RMII. Implementing a 100Mb PHY is not a trivial
task, this is why I was asking. I have seen an article at Comms Design:
http://www.commsdesign.com/showArticle.jhtml;jsessionid=FAG3F3AMSLDPQQSNDLQCKHSCJUNN2JVN?articleID=192200605
as a place to start but again it is MII to MII.

Thanks



----- Original Message -----
From: Guy Hutchison<ghutchis@g...>
To:
Date: Fri Jan 19 22:10:08 CET 2007
Subject: [oc] Implementing Ethernet PHY in Verilog

> On 1/19/07, attachment.htm
>
>