|
Message
From: Mikhail Matusov<misoma@r...>
Date: Fri Jan 19 22:24:43 CET 2007
Subject: [oc] Implementing Ethernet PHY in Verilog
On Fri, 19 Jan 2007 13:10:08 -0800
"Guy Hutchison" <ghutchis@g...> wrote:
> This one has me scratching my head. How do you connect an MII MAC to an
> RMII MAC? MII has 4 SDR data pins per direction, while RMII has 2 DDR pins
> per direction.
>
Xilinx has an appnote on how to convert GMII to RGMII. Basically you
just need a layer of external DDR registers with some simple logic. So,
I guess when the OP said the parts are connected back-to-back he omitted
this little detail. Personally I think adding a PHY layer in this
application would be a HUGE overkill.
/Mikhail
|
 |
Browse
