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Message
From: edb6628 at hotmail.com<edb6628@h...>
Date: Sat Jan 20 00:29:18 CET 2007
Subject: [oc] Implementing Ethernet PHY in Verilog
Hello,
I have inherited a design with two MACS connected to back to back.
One MAC interface is MII and the other is RMII. Both devices are
configured as MACs. Although, this violates the MII specification, it
is working, but I don't want to continue to press my luck.
I certainly can see an issue where the two MACs are MII compliant and
since the RX hold time of 10ns can not be guaranteed when TX is 0-25ns
from the rising edge of clock. This is the case with the network
processor on board:
NP RX setup=5.5ns hold=0ns
BME TX delay=0-25ns – no issue since NP hold =0
NP TX delay=17ns hold=2ns
BME RX setup=10ns hold=10ns – 8ns timing margin violation on hold time.
For MII compliant phys the RX sigs change on the falling-edge of the
clock so a violation is always avoided.
I am looking for either Verilog code or ideas on the best way to
implement Ethernet PHY functionality between these two devices.
Thank you
EB
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