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From: aniket at asic-architectinc.com<aniket@a...>
Date: Thu Jan 18 04:35:38 CET 2007
Subject: [oc] Physical design rules error during mapping with Xilinx8.1i
Hi

i am having problems with trying to generate a bitfile for my design.
I am using Xilinx 8.1i and it is reporting the following errors during
mapping and place and route.

ERROR: PhysDesignrules:760 - Incompatible programming for IO Standard.
IO Standard LVDS_25 of comp IO_x_x_x_X_x_x_x/iobuf_dqs/
IO does not allow both input and output programming on the same comp.

Does anyone know anything about this error?

Follow up	Author
[oc] Physical design rules error during mapping with Xilinx8.1i	Wesley J Landaker