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From: menchinidaniele at tiscali.it<menchinidaniele@t...>
Date: Sun Dec 10 11:38:05 CET 2006
Subject: [oc] DDR SDRAM Core
Hello,

I tried to use a Opencore DDR Sdram controller; I simulated it and
work well but when I syntetize it the core don't work.
For the syntesis I use XST in Xilinx Webpack 8.2i (SP3); and the board
that I use is Spartan 3E starter kit (the memory is a Micron with
512Mbit instead 256 Mbit but i see in the datasheet that the timing is
the same).
May I know if sameone have already do this?
If so, may I know wich is the things that I must change to achieve the
good syntesis?
Thank for all help.

Daniele