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From: menchinidaniele at tiscali.it<menchinidaniele@t...>
Date: Tue Nov 28 00:52:00 CET 2006
Subject: [oc] Controller DDR
Hello,

I try to use the Opencore DDR controller; the simulation work well in
all the conditions but when I put the bitstream in the Hardware the
controller don't work.
I syntesize the core with Xilinx ISE wabpack 8.2i and XST; may I know
if sameone already do this and in which mode? (do I need to set the
syntesis in a particular mode?)
My target is a Spartan3E family FPGA.
Thanks in advance for all.

Daniele