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Message
From: Kevin Somervill<kevin.m.somervill@n...>
Date: Tue Nov 21 16:26:44 CET 2006
Subject: [oc] Suggested extension to wishbone bus
| From: Richard Herveille [mailto:richard@h...]
| It allows for separate read/write buses in an SOC.
I got that part, but to what end is my question.
| This does improve performance, at the cost of increased area.
How do you figure it increases performance? If device A is reading device
B, can device C also write to it? Not many cores support concurrent access
nor do typical bus structures. Are you implying a cross bar type
functionality where device C would write to device D while A is reading B?
You don't need to separate the bus out to get that. Is there a particular
application you envision for this?
| Providing a separate wb_re_i does not provide any benefits
| and is utterly
| redundant.
I wouldn't say that (else I wouldn't have made the comment). I'd bet a lot
folks generate (implicitly or explicitly) read enable and write enable lines
from the single we_i signal. Synthesis tools as well will optimize a signal
to a bunch of inverters to a signal to a single inverter that is fanned out.
./ks
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