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Message
From: Richard Herveille<richard@h...>
Date: Tue Nov 21 16:04:40 CET 2006
Subject: [oc] Suggested extension to wishbone bus
It allows for separate read/write buses in an SOC.
This does improve performance, at the cost of increased area.
Providing a separate wb_re_i does not provide any benefits and is utterly
redundant.
Richard
-----Original Message-----
From: cores-bounces@o... [mailto:cores-bounces@o...] On
Behalf Of Kevin Somervill
Sent: Tuesday, November 21, 2006 2:58 PM
To: 'Discussion list about free open source IP cores'
Subject: RE: [oc] Suggested extension to wishbone bus
Hello,
| From: cores-bounces@o...
| I've been thinking about extending the Wishbone bus.
|
| The extension, called Wishbone Duplex, features separate
| read/write sections;
<snip>
| As you can see 'wb_we_i' has been removed, as it's not
| required anymore.
|
| Wishbone Duplex is an extension to the Wishbone standard. A
| Wishbone Duplex core can be connected to a Wishbone Classic
| or Wishbone RevB.3 bus using a simple wrapper.
| Any ideas/suggestions?
What is the expected benefit of doing this? I can see splitting out just
the rd and wr lines as wb_re_i and wb_we_i, but I don't see the value in
splitting out all of interface ports. It doesn't seem simplify the
interconnect or improve performance that I can see. It's also somewhat of a
divergence from standard interfaces with rd/wr lines. What exactly are you
trying to address with the extension?
Thanks,
./ks
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