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From: Mark McDougall<markm@v...>
Date: Thu Sep 28 04:07:38 CEST 2006
Subject: [oc] IrDA SIR - not working???
Hi,

Has anyone here successfully used the SIR-only mode IrDA core?

Because from what I'm seeing, it doesn't actually work!?!

The testbench appears to work because the tx and rx ends are clocked by
the same clock and also come out of reset at the same time.

But in my simulation, the tx and rx ends are clocked asynchronously and
also come out of reset at different times. The first few characters are
transmitted and received correctly but then a 'bug' shows itself.

The problem occurs in the irda_sir_decoder.v module when the counter
transitions to 15 right in the middle of a zero pulse on the incoming
stream. In this case 'zero' glitches and on the *next* wrap of the
counter it's the wrong state to correctly decode a one.

Has anyone else come across this???
Can the author comment?

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

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[oc] IrDA SIR - not working???	Mark McDougall