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Hi Martin,
I am here with new questions :).

As per our disussion yesterday,I used jopsim,after that I gave "doit test
test Helloworld",when i tried to simulate "sim" command and found the result
positive.
Now when i tried the modified scio block which inludes sc2wb in it,it is
giving the error at the end in scio block.

Below I am pasting the part of simulation result when executed on DOS.
Can you please tell me how to include the work library of sc2wb and i2S  for
simulation..

.
C:\newjop\jop\modelsim>sim

C:\newjop\jop\modelsim>set jopdir=../vhdl

C:\newjop\jop\modelsim>rem set options=-93 -quiet -check_synthesis -lint
-pedant
icerrors

C:\newjop\jop\modelsim>set options=-93 -quiet

C:\newjop\jop\modelsim>rmdir /S/Q work
The system cannot find the file specified.

C:\newjop\jop\modelsim>vlib work

C:\newjop\jop\modelsim>vcom -93 -quiet
../vhdl/simulation/sim_jop_config_100.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/top/jop_types.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/simulation/sim_ram.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/simulation/sim_pll.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/simulation/sim_jbc.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/simulation/sim_rom.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/simulation/sim_memory.vhd

C:\newjop\jop\modelsim>rem vcom -93 -quiet ../vhdl/scio/fifo.vhd

C:\newjop\jop\modelsim>rem vcom -93 -quiet ../vhdl/scio/sc_uart.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/simulation/sim_sc_uart.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/wishbone/wb_pack.vhd

C:\newjop\jop\modelsim>rem vcom -93 -quiet
../vhdl/wishbone/wb_test_slave.vhd

C:\newjop\jop\modelsim>rem vcom -93 -quiet ../vhdl/wishbone/wb_top.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/jtbl.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/offtbl.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/core/cache.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/memory/sc_sram32_flash.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/memory/mem_sc.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/core/mul.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/core/extension.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/core/bcfetch.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/core/fetch.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/core/decode.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/core/shift.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/core/stack.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/core/core.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/scio/sc_cnt.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/scio/scio_min.vhd
** Error: (vcom-11) Could not find work.sc2wb.
** Error: ../vhdl/scio/scio_min.vhd(266): (vcom-1195) Cannot find expanded
name:
 'work.sc2wb'.
** Error: ../vhdl/scio/scio_min.vhd(266): Unknown record element "sc2wb".
** Error: ../vhdl/scio/scio_min.vhd(287): Statement cannot be labeled.
** Error: ../vhdl/scio/scio_min.vhd(364): VHDL Compiler exiting

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/top/jopcyc.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/simulation/tb_jop.vhd

C:\newjop\jop\modelsim>pause Start simulation?
Press any key to continue . . .

C:\newjop\jop\modelsim>vsim -do sim.do tb_jop
Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl

C:\newjop\jop\modelsim>cd ..

C:\newjop\jop>

Martin Schoeberl wrote:
> 
> Hi Tan,
> 
>> That was not my intention Martin. I had to resort to asking you to have a
>> look at my code as I had no other option and I was unable to clearly
>> explain
>> my problem. I thought showing you my code would give you an idea of the
>> problem.
> 
> You could upload your code to a website and provde a link to it
> in the posting. That's a less intrusive way ;-)
> 
>> As per your advice yesterday, I enabled the mem_sc_if.vhd back. If you
>> remember you had once advised me to change the scio_dspio.vhd. I had
>> changed
>> it by replacing the ac97 component with I2S.Additionally the
>> scio_dspio.vhd
>> had a counter,a UART, a usb and  sc2wb. Since I wanted to use only sc2wb,
>> I
>> disabled  the UART and the USB blocks.
> 
> Do you want to run your design in hardware (FPGA) or just in
> a ModelSim simulation?
> 
> If you want to run it in an FPGA you need the UART. How would
> you download the Java program without a communication path
> between your PC and JOP?
> 
> Even in the ModelSim simulation the UART makes sense. You
> can debug your Java program with print outs. System.out.println()
> goes to the UART.
> 
> So, there is no reason to remove the UART from the design.
> 
>> I am pasting the modified code below:
>> -- SimpCon Wishbone bridge
>> cmp_wb: entity work.sc2wb generic map (
>> addr_bits => SLAVE_ADDR_BITS
>> )
>> port map(
>> clk => clk,
>> reset => reset,
>> address => address(SLAVE_ADDR_BITS-1 downto 0),
>> wr_data => wr_data,
>> rd => sc_rd(1),
>> wr => sc_wr(1),
>> rd_data => sc_dout(1),
>> rdy_cnt => sc_rdy_cnt(1),
>> wb_out => wb_out,
>> wb_in => wb_in );
> 
> looks ok, that's the same as in scio_dspio.vhd.
> 
>>   tx_i2s_sck             :  out std_logic;
>> tx_i2s_sd : out std_logic;
>> tx_i2s_ws : out std_logic;
>> tx_i2s_int :out  std_logic;
> 
> looks, like you are only using transmit. No receive
> port, right?
> 
>> This is the top module entity.The synthesis works fine but during
>> simulation,when I force the value to wr_data,there is no respone from
>> tx_i2s_sd. Do you see anything obviously wrong in what I have done?
> 
> Yes, this is the main issue.
> 
> Think about a processor (JOP is a processor). When you force just
> a value on the data bus, where the processor usually reads instructions
> and reads and writes values. What you you think what the processor
> will do?
> 
> JOP (and each processor) will do nothing usefull without a program!
> So you have to write your application (for JOP in Java) and download
> it to the RAM.
> 
> Start with a simple 'Hello World' and run this in the simulation
> or on the real hardware. Use the unmodified code first!!!
> 
> Than add your I2S interface and see if 'Hello World' still
> runns.
> 
> That's my way to perform changes to a unknown project. First
> get it unmodified running THAN apply the changes. I do this
> even when I'm working with JOP - first a clean, working
> strating point.
> 
> Cheers,
> Martin
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores
> 
> 

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