Message

Reply | Reply all

Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

From: Ielsch Francis<francis.ielsch@e...>
Date: Fri Jan 13 07:53:24 CET 2006
Subject: AW: [oc] Wishbone in UART16550
Hi Henri,

I think it does only exist in verilog and if your design is already written VHDL then you have to mix VHDL and verilog.

Fran6

-----Ursprüngliche Nachricht-----
Von: cores