OPENCORES.ORG

I did the same thing you are trying to do.

I tried it about a year ago, and never did get it to work.  IIRC it
didn't support burst read/writes at the time either, but that may have
changed.  I ended up trying to rip out the controller from the EDK
core and wrote an OPB wrapper to talk to it, but that also didn't work
on hardware.  (This was for a school project, so we gave up on DDR at
the end of the semester).

I hope you have much better luck then I did.
Mike

On 12/13/05, jihoon@m... <jihoon@m...> wrote:
> I did the same thing you are trying to do.
> But I think it's too late.
> If you have any question, send me an email.
>
> /Jihoon
>
> ----- Original Message -----
> From: Anna D. Ashley<ada@c...>
> To:
> Date: Mon Aug 29 17:19:33 CEST 2005
> Subject: [oc] DDR SDRAM controller
>
> > Hi all,
> >
> > meanwhile I had some questions from some of you about my problem
> > and
> > solutions. Unfortunately I have not solved this problem and it
> > seems to
> > be no solution. MIG007 works with a couple of test boards supported
> > by
> > Xilinx and does not work with the rest (or I could not find out how
> > to
> > bring it to work). So I switched to the open cores DDR SDRAM
> > controller
> > design but it is going not so fast because there is no any
> > help\documentation\support.
> > If someone would solve the problem just let me know.
> > Also if someone has already used open cores controller please tell
> > me.
> > Best,
> >  Anna
> > xjf77 at opencores.org wrote:
> > >Hi, Anna,
> > > I am also working on DDR SDRAM Controller. Would you please
> > tell me
> > >if you have solved this problem? If yes, which tool did you
> > use? MIG007
> > >or open core from here?
> > > Cheers,
> > >xjf77
> > >
> > >----- Original Message -----
> > >From: ada at cwazy.co.uk<ada at c...>
> > >To:
> > >Date: Wed Aug 10 12:06:43 CEST 2005
> > >Subject: [oc] DDR SDRAM controller
> > >
> > >
> > >
> >
> >
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>