LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Sponsors
  • Mirrors
  • Logos
  • Contact us
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Navigation: All forums > Cores > Message List > Message Post

    Message

    Reply | Reply all
    Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

    From: Guy Hutchison<ghutchis@g...>
    Date: Thu Dec 8 04:15:26 CET 2005
    Subject: [oc] T80 bugfix for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
    Top
    Hi Peter,

    We spoke a while back, and you mentioned the JR bug recently on the
    list. I had a little time today to look in to it, and was wondering
    if you could elaborate on what the bug is.

    According to the Z80 handbook, the cycle timing for a JR operation is
    4/3 if the test fails, and 4/3/5 if the test passes. This matches the
    mcycle coding in the microcode as well as the results I see in
    simulation.

    Could you (re)summarize the problem for me?

    Thanks,

    Guy

    Follow upAuthor
    [oc] Re: T80 bugfix for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDRMr mike johnson

     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.