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Message
From: Tim Tait<tim.tait1@g...>
Date: Mon Nov 28 07:30:02 CET 2005
Subject: [oc] lack of pipeline in wishbone (resend)
Does anyone else see it as a serious shortcoming that Wishbone does not
support Address/Data pipelining?
When connecting Wishbone to standard synchronous SRAM's (that register
all address/control inputs) it makes it impossible to maintain
throughput at full clock rate on random address sequences, even for
those with flow-through data.
The "FASM" Synchronous RAM model that is discussed in the spec if not
actually synchonrous during read, only during write. This does not match
any SSRAM IC I have encountered, or the SSRAM's inside recent Altera FPGA's.
Is anyone working on an extension to WB to support pipelining?
Tim
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