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Message
From: rpaley_yid at yahoo.com<rpaley_yid@y...>
Date: Mon Nov 7 22:38:49 CET 2005
Subject: [oc] single_port: replace rnw input by nce, noe and nwe inputs
Hi,I agree. Please update the documentation and timing diagrams. ----- Original Message -----
From: Michael Geng<vhdl@M...>
To:
Date: Sat Nov 5 12:06:03 CET 2005
Subject: [oc] single_port: replace rnw input by nce, noe and nwe
inputs
> Hi Robert (or other users interrested to the single_port model),
>
> the single_port core presently only has a rnw input signal. That's
> different to real asynchronous RAMs as you can buy them. They
> usually have the following signals.
> nce (not chip enable)
> noe (not output enable)
> nwe (not write enable)
> I think it would be useful to change the interface in this way.
> The model would then also contain tristate drivers as real RAMs
> have. In my present design I had to implement these tristate
> drivers externally. So I could simplify my design by adding the
> above interface. I think this would also be the case for most
> other people who want to simulate an external asynchronous RAM.
> How do you think about it?
> Michael
>
>
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