OPENCORES.ORG

Subject: [oc] what opensource tools to use

On Tue, 1 Mar 2005 19:14:29 +0100, winglion@2...>
> Subject: [oc] what opensource tools to use
> To: "cores" <cores@o...>
> Message-ID: <0S949773839282.00439@s...>
> Content-Type: text/plain;       charset="gb2312"
> 
> I fount that 80% of gays here vote to use opensource tools
> For me ,It's a real new idea.
> please tell me what opensource sofewate you use for disigning a core(sim, syn )
> and sch pcb tool!
> 
> ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡winglion@2...
> ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡2005-02-26
> 
> ------------------------------
> 
> Message: 3
> Date: Sat, 26 Feb 2005 14:24:22 -0500
> From: Mike Delaney <mmdst23@g...>
> Subject: Re: [oc] what opensource tools to use
> To: Discussion list about free open source IP cores
>        <cores@o...>
> Message-ID: <ea9d9b97050226112454db2e48@m...>
> Content-Type: text/plain; charset=UTF-8
> 
> For designing a core, that's a hard question.  Did you look at the EDA
> Tools list on the opencores site,
> http://www.opencores.org/projects.cgi/web/edatools/eda_tools ?
> I think there is at least one free (beer) simulator, and there is at
> least one open source simulator, but I'm not sure how they work.  From
> the web site of one I found (after quickly trying a couple of the
> links) "TyVIS allows you to simulate and execute VHDL code that has
> been translated into the TyVIS C++ intermediate form."  I took a quick
> look at the manual, but it seems to suggest that using vendor-spefic
> parts, such as block RAMs, or ASIC multipliers or DSP blocks/slices,
> *might* be possible but it's not mentioned in the manual (at least
> it's not in the table of contents).
> 
> I've never seen an open source synthesis tool, except for one project
> that's been dead for a long time.  Maybe take a look at this:
> http://www.opencores.org/forums.cgi/cores/2004/05/000757
> 
> Honestly, I'm not even aware of a free (beer and legal) version of the
> tools from either Xilinx or Altera, although they both have a free
> windows version that includes a special (ie. SLOW) version of
> ModelSim.  I've heard rumors that the next Xilinx release will have a
> Linux version of Webpack, but even if true, it won't be out until May.
> However, Webpack dosen't support all of the Xilinx chips and lacks
> some of the other features of the full Xilinx tools, which do have a
> current Linux port, but it costs about $2.5k
> 
> For a PCB Tool, check out gEDA.
> 
> Mike
> 
> On Sat, 26 Feb 2005 16:05:07 +0800, é"çŸ³ <winglion@2...> wrote:
> > I fount that 80% of gays here vote to use opensource tools
> > For me ,It's a real new idea.
> > please tell me what opensource sofewate you use for disigning a core(sim, syn )
> > and sch pcb tool!
> >
> > winglion@2...
> > 2005-02-26
> >
> > _______________________________________________
> > http://www.opencores.org/mailman/listinfo/cores
> >
> 
> ------------------------------
> 
> Message: 4
> Date: Sat, 26 Feb 2005 14:53:12 -0500
> From: "Michael Hordijk" <hoffbrinkle@h...>
> Subject: [oc] Re: what opensource tools to use
> To: cores@o...
> Message-ID: <cvqk2q$aqa$1@s...>
> 
> > I think there is at least one free (beer) simulator, and there is at
> > least one open source simulator, but I'm not sure how they work.  From
> 
>    I've been using GHDL as much as I can for simulation.  It's effective,
> and pretty robust considering it's not that old.  There's not much it can't
> do (it can run a DLX processor and the LEON1 SPARC processor).  It's a
> native VHDL compiler (i.e. it does not translate to intermediate C/C++ or
> anything).  It's written in ADA as a front end to GCC.  The developer is
> easy to get a hold of and responsive to fixing bugs, and it's being actively
> developed.  http://ghdl.free.fr
> 
> > look at the manual, but it seems to suggest that using vendor-spefic
> > parts, such as block RAMs, or ASIC multipliers or DSP blocks/slices,
> 
>    I've had no problems using the above simulator with any of the Xilinx
> cores I use.  Obviously, inferred parts are no problem.  It's compiled
> everything I need from unisim and XilinxCoreLib with no problems.  Supports
> VHDL 2002, etc.
> 
>    I would highly recommend it as an alternative.  I haven't gotten to
> using it on a large design, so I can't say how fast or slow it is compared
> to, say, ModelSim or what have you.  But "free" goes a long, long, long way
> to making up for that.  Think how much computing resources you could buy for
> the cost of single SE floating license...
> 
> - hoffer
> 
> ------------------------------
> 
> Message: 5
> Date: Sat, 26 Feb 2005 17:31:11 -0500
> From: Mike Delaney <mmdst23@g...>
> Subject: Re: [oc] Re: what opensource tools to use
> To: Discussion list about free open source IP cores
>        <cores@o...>
> Message-ID: <ea9d9b97050226143163ae6b22@m...>
> Content-Type: text/plain; charset=US-ASCII
> 
> Doh!  I forgot that Xilinx gave out the source to the behavioral
> libraries for all the ASIC cells.  Sorry about that.
> 
> Mike
> 
> On Sat, 26 Feb 2005 14:53:12 -0500, Michael Hordijk
> <hoffbrinkle@h...> wrote:
> > <cut>
> > > look at the manual, but it seems to suggest that using vendor-spefic
> > > parts, such as block RAMs, or ASIC multipliers or DSP blocks/slices,
> >
> >     I've had no problems using the above simulator with any of the Xilinx
> > cores I use.  Obviously, inferred parts are no problem.  It's compiled
> > everything I need from unisim and XilinxCoreLib with no problems.  Supports
> > VHDL 2002, etc.
> >
> 
> ------------------------------
> 
> Message: 6
> Date: Sun, 27 Feb 2005 10:15:32 +0100
> From: "Richard Herveille" <richard@h...>
> Subject: RE: [oc] I2C Core RTL Simulation / FPGA mismatch...
> To: <jeff@l...>, "'Discussion list about free open source IP
>        cores'" <cores@o...>
> Message-ID: <20050227092816.18FDE862F0@m...>
> Content-Type: text/plain;       charset="us-ascii"
> 
> Hi Jeff,
> 
> >           if (wb_wacc)
> >             case (wb_adr_i) // synopsys full_case parallel_case
> >                3'b000 : prer [ 7:0] <= #1 wb_dat_i;
> >                3'b001 : prer [15:8] <= #1 wb_dat_i;
> >                3'b010 : ctr         <= #1 wb_dat_i;
> >                3'b011 : txr         <= #1 wb_dat_i;
> >             endcase
> >
> > Does the // synopsys full_case parallel_case not tell the
> > synthesis tool that ALL the cases are listed?  All other
> > cases are considered "don't care" by the synthesis tool, right?
> 
> Sorta.
> 
> >
> > The "cr" register is mapped at address 3'b100.  This case is
> > not listed in the case statment, so this bit is optimized
> > away and is not considered important.
> >
> > That's the problem... now when address 3'b100 is written, the
> > case statement sees it as 3'bx00 and the prer(7:0) is written
> > as well as cr.
> 
> You're right. I fixed it and uploaded a new version.
> I also fixed the scl/sda delay issue in the testbench.
> 
> > Does the case statement not need a default line which keeps
> > the previous values for the 4 registers?  Am I
> > misunderstanding this concept?
> 
> You either use the full_case statement, or you add a default statement.
> In this case we need the default statement.
> 
> Please download the latest version from OpenCores.
> 
> Cheers,
> Richard
> 
> ------------------------------
> 
> Message: 7
> Date: Tue, 01 Mar 2005 14:06:57 +0200
> From: Nikolaos Kavvadias <nkavv@p...>
> Subject: Re: [oc] Re: what opensource tools to use
> To: Discussion list about free open source IP cores
>        <cores@o...>
> Message-ID: <42245AE1.4050101@p...>
> Content-Type: text/plain; charset=ISO-8859-1
> 
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
> 
> Mike Delaney wrote:
> 
> > Doh! I forgot that Xilinx gave out the source to the behavioral
> > libraries for all the ASIC cells. Sorry about that.
> 
> Please, could you refine on your statement? Any links to the Xilinx
> stuff???
> 
> > On Sat, 26 Feb 2005 14:53:12 -0500, Michael Hordijk
> > <hoffbrinkle@h...> wrote:
> >
> >> <cut>
> >>
> >>> look at the manual, but it seems to suggest that using
> >>> vendor-spefic parts, such as block RAMs, or ASIC multipliers or
> >>> DSP blocks/slices,
> >>
> >> I've had no problems using the above simulator with any of the
> >> Xilinx cores I use. Obviously, inferred parts are no problem.
> >> It's compiled everything I need from unisim and XilinxCoreLib
> >> with no problems. Supports VHDL 2002, etc.
> >>
> > _______________________________________________
> > http://www.opencores.org/mailman/listinfo/cores
> >
> >
> >
> 
> -----BEGIN PGP SIGNATURE-----
> Version: GnuPG v1.4.0 (MingW32)
> Comment: Using GnuPG with Thunderbird - http://enigmail.mozdev.org
> 
> iD8DBQFCJFrhMPiy0tCWlz4RApCaAKCdV9ZCpUG3PiIZyNfPwri5RCpXRQCeOx+V
> uncMRLR4G3C54AZYU0+TcP0=
> =XBHb
> -----END PGP SIGNATURE-----
> 
> ------------------------------
> 
> Message: 8
> Date: Tue, 1 Mar 2005 09:59:48 -0500
> From: Mike Delaney <mmdst23@g...>
> Subject: Re: [oc] Re: what opensource tools to use
> To: Discussion list about free open source IP cores
>        <cores@o...>
> Message-ID: <ea9d9b97050301065932beac9c@m...>
> Content-Type: text/plain; charset=US-ASCII
> 
> On Tue, 01 Mar 2005 14:06:57 +0200, Nikolaos Kavvadias
> <nkavv@p...> wrote:
> > -----BEGIN PGP SIGNED MESSAGE-----
> > Hash: SHA1
> >
> > Mike Delaney wrote:
> >
> > > Doh! I forgot that Xilinx gave out the source to the behavioral
> > > libraries for all the ASIC cells. Sorry about that.
> >
> > Please, could you refine on your statement? Any links to the Xilinx
> > stuff???
> 
> Well, the only way I know of (for free) is to download Xilinx Webpack
> and install it.  Look in the $XILINX/vhdl/src directory.  So you'll
> still need a Windows box, but the source is also included with the
> other (costly) versions of the Xilinx tools.  I'm not sure if they do
> have a seperate download for it or not.
> 
> >
> > > On Sat, 26 Feb 2005 14:53:12 -0500, Michael Hordijk
> > > <hoffbrinkle@h...> wrote:
> > >
> > >> <cut>
> > >>
> > >>> look at the manual, but it seems to suggest that using
> > >>> vendor-spefic parts, such as block RAMs, or ASIC multipliers or
> > >>> DSP blocks/slices,
> > >>
> > >> I've had no problems using the above simulator with any of the
> > >> Xilinx cores I use. Obviously, inferred parts are no problem.
> > >> It's compiled everything I need from unisim and XilinxCoreLib
> > >> with no problems. Supports VHDL 2002, etc.
> > >>
> > > _______________________________________________
> > > http://www.opencores.org/mailman/listinfo/cores
> > >
> > >
> > >
> >
> > -----BEGIN PGP SIGNATURE-----
> > Version: GnuPG v1.4.0 (MingW32)
> > Comment: Using GnuPG with Thunderbird - http://enigmail.mozdev.org
> >
> > iD8DBQFCJFrhMPiy0tCWlz4RApCaAKCdV9ZCpUG3PiIZyNfPwri5RCpXRQCeOx+V
> > uncMRLR4G3C54AZYU0+TcP0=
> > =XBHb
> > -----END PGP SIGNATURE-----
> >
> >
> > _______________________________________________
> > http://www.opencores.org/mailman/listinfo/cores
> >
> 
> ------------------------------
> 
> Message: 9
> Date: Tue, 1 Mar 2005 09:53:49 -0800
> From: "Sheila Carey" <sheilapcarey@d...>
> Subject: RE: [oc] Re: what opensource tools to use
> To: "'Mike Delaney'" <mmdst23@g...>,       "'Discussion list about free
>        open source IP cores'" <cores@o...>
> Message-ID: <20050301175353.4976.3932@h...>
> Content-Type: text/plain;       charset="US-ASCII"
> 
> And you'll find 16 Xilinx training sessions (free) here:
> 
> http://www.demosondemand.com/dod/proddemos/vendors/pd_xilinx.aspx
> 
> -----Original Message-----
> From: cores-bounces@o... [mailto:cores-bounces@o...] On
> Behalf Of Mike Delaney
> Sent: Tuesday, March 01, 2005 7:00 AM
> To: Discussion list about free open source IP cores
> Subject: Re: [oc] Re: what opensource tools to use
> 
> On Tue, 01 Mar 2005 14:06:57 +0200, Nikolaos Kavvadias
> <nkavv@p...> wrote:
> > -----BEGIN PGP SIGNED MESSAGE-----
> > Hash: SHA1
> >
> > Mike Delaney wrote:
> >
> > > Doh! I forgot that Xilinx gave out the source to the behavioral
> > > libraries for all the ASIC cells. Sorry about that.
> >
> > Please, could you refine on your statement? Any links to the Xilinx
> > stuff???
> 
> Well, the only way I know of (for free) is to download Xilinx Webpack and
> install it.  Look in the $XILINX/vhdl/src directory.  So you'll still need a
> Windows box, but the source is also included with the other (costly)
> versions of the Xilinx tools.  I'm not sure if they do have a seperate
> download for it or not.
> 
> >
> > > On Sat, 26 Feb 2005 14:53:12 -0500, Michael Hordijk
> > > <hoffbrinkle@h...> wrote:
> > >
> > >> <cut>
> > >>
> > >>> look at the manual, but it seems to suggest that using
> > >>> vendor-spefic parts, such as block RAMs, or ASIC multipliers or
> > >>> DSP blocks/slices,
> > >>
> > >> I've had no problems using the above simulator with any of the
> > >> Xilinx cores I use. Obviously, inferred parts are no problem.
> > >> It's compiled everything I need from unisim and XilinxCoreLib with
> > >> no problems. Supports VHDL 2002, etc.
> > >>
> > > _______________________________________________
> > > http://www.opencores.org/mailman/listinfo/cores
> > >
> > >
> > >
> >
> > -----BEGIN PGP SIGNATURE-----
> > Version: GnuPG v1.4.0 (MingW32)
> > Comment: Using GnuPG with Thunderbird - http://enigmail.mozdev.org
> >
> > iD8DBQFCJFrhMPiy0tCWlz4RApCaAKCdV9ZCpUG3PiIZyNfPwri5RCpXRQCeOx+V
> > uncMRLR4G3C54AZYU0+TcP0=
> > =XBHb
> > -----END PGP SIGNATURE-----
> >
> >
> > _______________________________________________
> > http://www.opencores.org/mailman/listinfo/cores
> >
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores
> 
> ------------------------------
> 
> _______________________________________________
> Cores mailing list
> Cores@o...
> cores
> 
> ------------------------------
> 
> Message: 2
> Date: Sat, 26 Feb 2005 16:05:07 +0800
> From: "=?gb2312?B?zPrKrw==?=" <winglion@2...>
> Subject: [oc] what opensource tools to use
> To: "cores" <cores@o...>
> Message-ID: <0S949773839282.00439@s...>
> Content-Type: text/plain;       charset="gb2312"
> 
> I fount that 80% of gays here vote to use opensource tools
> For me ,It's a real new idea.
> please tell me what opensource sofewate you use for disigning a core(sim, syn )
> and sch pcb tool!
> 
> ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡winglion@2...
> ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡2005-02-26
> 
> ------------------------------
> 
> Message: 3
> Date: Sat, 26 Feb 2005 14:24:22 -0500
> From: Mike Delaney <mmdst23@g...>
> Subject: Re: [oc] what opensource tools to use
> To: Discussion list about free open source IP cores
>        <cores@o...>
> Message-ID: <ea9d9b97050226112454db2e48@m...>
> Content-Type: text/plain; charset=UTF-8
> 
> For designing a core, that's a hard question.  Did you look at the EDA
> Tools list on the opencores site,
> http://www.opencores.org/projects.cgi/web/edatools/eda_tools ?
> I think there is at least one free (beer) simulator, and there is at
> least one open source simulator, but I'm not sure how they work.  From
> the web site of one I found (after quickly trying a couple of the
> links) "TyVIS allows you to simulate and execute VHDL code that has
> been translated into the TyVIS C++ intermediate form."  I took a quick
> look at the manual, but it seems to suggest that using vendor-spefic
> parts, such as block RAMs, or ASIC multipliers or DSP blocks/slices,
> *might* be possible but it's not mentioned in the manual (at least
> it's not in the table of contents).
> 
> I've never seen an open source synthesis tool, except for one project
> that's been dead for a long time.  Maybe take a look at this:
> http://www.opencores.org/forums.cgi/cores/2004/05/000757
> 
> Honestly, I'm not even aware of a free (beer and legal) version of the
> tools from either Xilinx or Altera, although they both have a free
> windows version that includes a special (ie. SLOW) version of
> ModelSim.  I've heard rumors that the next Xilinx release will have a
> Linux version of Webpack, but even if true, it won't be out until May.
> However, Webpack dosen't support all of the Xilinx chips and lacks
> some of the other features of the full Xilinx tools, which do have a
> current Linux port, but it costs about $2.5k
> 
> For a PCB Tool, check out gEDA.
> 
> Mike
> 
> On Sat, 26 Feb 2005 16:05:07 +0800, é"çŸ³ <winglion@2...> wrote:
> > I fount that 80% of gays here vote to use opensource tools
> > For me ,It's a real new idea.
> > please tell me what opensource sofewate you use for disigning a core(sim, syn )
> > and sch pcb tool!
> >
> > winglion@2...
> > 2005-02-26
> >
> > _______________________________________________
> > http://www.opencores.org/mailman/listinfo/cores
> >
> 
> ------------------------------
> 
> Message: 4
> Date: Sat, 26 Feb 2005 14:53:12 -0500
> From: "Michael Hordijk" <hoffbrinkle@h...>
> Subject: [oc] Re: what opensource tools to use
> To: cores@o...
> Message-ID: <cvqk2q$aqa$1@s...>
> 
> > I think there is at least one free (beer) simulator, and there is at
> > least one open source simulator, but I'm not sure how they work.  From
> 
>    I've been using GHDL as much as I can for simulation.  It's effective,
> and pretty robust considering it's not that old.  There's not much it can't
> do (it can run a DLX processor and the LEON1 SPARC processor).  It's a
> native VHDL compiler (i.e. it does not translate to intermediate C/C++ or
> anything).  It's written in ADA as a front end to GCC.  The developer is
> easy to get a hold of and responsive to fixing bugs, and it's being actively
> developed.  http://ghdl.free.fr
> 
> > look at the manual, but it seems to suggest that using vendor-spefic
> > parts, such as block RAMs, or ASIC multipliers or DSP blocks/slices,
> 
>    I've had no problems using the above simulator with any of the Xilinx
> cores I use.  Obviously, inferred parts are no problem.  It's compiled
> everything I need from unisim and XilinxCoreLib with no problems.  Supports
> VHDL 2002, etc.
> 
>    I would highly recommend it as an alternative.  I haven't gotten to
> using it on a large design, so I can't say how fast or slow it is compared
> to, say, ModelSim or what have you.  But "free" goes a long, long, long way
> to making up for that.  Think how much computing resources you could buy for
> the cost of single SE floating license...
> 
> - hoffer
> 
> ------------------------------
> 
> Message: 5
> Date: Sat, 26 Feb 2005 17:31:11 -0500
> From: Mike Delaney <mmdst23@g...>
> Subject: Re: [oc] Re: what opensource tools to use
> To: Discussion list about free open source IP cores
>        <cores@o...>
> Message-ID: <ea9d9b97050226143163ae6b22@m...>
> Content-Type: text/plain; charset=US-ASCII
> 
> Doh!  I forgot that Xilinx gave out the source to the behavioral
> libraries for all the ASIC cells.  Sorry about that.
> 
> Mike
> 
> On Sat, 26 Feb 2005 14:53:12 -0500, Michael Hordijk
> <hoffbrinkle@h...> wrote:
> > <cut>
> > > look at the manual, but it seems to suggest that using vendor-spefic
> > > parts, such as block RAMs, or ASIC multipliers or DSP blocks/slices,
> >
> >     I've had no problems using the above simulator with any of the Xilinx
> > cores I use.  Obviously, inferred parts are no problem.  It's compiled
> > everything I need from unisim and XilinxCoreLib with no problems.  Supports
> > VHDL 2002, etc.
> >
> 
> ------------------------------
> 
> Message: 6
> Date: Sun, 27 Feb 2005 10:15:32 +0100
> From: "Richard Herveille" <richard@h...>
> Subject: RE: [oc] I2C Core RTL Simulation / FPGA mismatch...
> To: <jeff@l...>, "'Discussion list about free open source IP
>        cores'" <cores@o...>
> Message-ID: <20050227092816.18FDE862F0@m...>
> Content-Type: text/plain;       charset="us-ascii"
> 
> Hi Jeff,
> 
> >           if (wb_wacc)
> >             case (wb_adr_i) // synopsys full_case parallel_case
> >                3'b000 : prer [ 7:0] <= #1 wb_dat_i;
> >                3'b001 : prer [15:8] <= #1 wb_dat_i;
> >                3'b010 : ctr         <= #1 wb_dat_i;
> >                3'b011 : txr         <= #1 wb_dat_i;
> >             endcase
> >
> > Does the // synopsys full_case parallel_case not tell the
> > synthesis tool that ALL the cases are listed?  All other
> > cases are considered "don't care" by the synthesis tool, right?
> 
> Sorta.
> 
> >
> > The "cr" register is mapped at address 3'b100.  This case is
> > not listed in the case statment, so this bit is optimized
> > away and is not considered important.
> >
> > That's the problem... now when address 3'b100 is written, the
> > case statement sees it as 3'bx00 and the prer(7:0) is written
> > as well as cr.
> 
> You're right. I fixed it and uploaded a new version.
> I also fixed the scl/sda delay issue in the testbench.
> 
> > Does the case statement not need a default line which keeps
> > the previous values for the 4 registers?  Am I
> > misunderstanding this concept?
> 
> You either use the full_case statement, or you add a default statement.
> In this case we need the default statement.
> 
> Please download the latest version from OpenCores.
> 
> Cheers,
> Richard
> 
> ------------------------------
> 
> Message: 7
> Date: Tue, 01 Mar 2005 14:06:57 +0200
> From: Nikolaos Kavvadias <nkavv@p...>
> Subject: Re: [oc] Re: what opensource tools to use
> To: Discussion list about free open source IP cores
>        <cores@o...>
> Message-ID: <42245AE1.4050101@p...>
> Content-Type: text/plain; charset=ISO-8859-1
> 
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
> 
> Mike Delaney wrote:
> 
> > Doh! I forgot that Xilinx gave out the source to the behavioral
> > libraries for all the ASIC cells. Sorry about that.
> 
> Please, could you refine on your statement? Any links to the Xilinx
> stuff???
> 
> > On Sat, 26 Feb 2005 14:53:12 -0500, Michael Hordijk
> > <hoffbrinkle@h...> wrote:
> >
> >> <cut>
> >>
> >>> look at the manual, but it seems to suggest that using
> >>> vendor-spefic parts, such as block RAMs, or ASIC multipliers or
> >>> DSP blocks/slices,
> >>
> >> I've had no problems using the above simulator with any of the
> >> Xilinx cores I use. Obviously, inferred parts are no problem.
> >> It's compiled everything I need from unisim and XilinxCoreLib
> >> with no problems. Supports VHDL 2002, etc.
> >>
> > _______________________________________________
> > http://www.opencores.org/mailman/listinfo/cores
> >
> >
> >
> 
> -----BEGIN PGP SIGNATURE-----
> Version: GnuPG v1.4.0 (MingW32)
> Comment: Using GnuPG with Thunderbird - http://enigmail.mozdev.org
> 
> iD8DBQFCJFrhMPiy0tCWlz4RApCaAKCdV9ZCpUG3PiIZyNfPwri5RCpXRQCeOx+V
> uncMRLR4G3C54AZYU0+TcP0=
> =XBHb
> -----END PGP SIGNATURE-----
> 
> ------------------------------
> 
> Message: 8
> Date: Tue, 1 Mar 2005 09:59:48 -0500
> From: Mike Delaney <mmdst23@g...>
> Subject: Re: [oc] Re: what opensource tools to use
> To: Discussion list about free open source IP cores
>        <cores@o...>
> Message-ID: <ea9d9b97050301065932beac9c@m...>
> Content-Type: text/plain; charset=US-ASCII
> 
> On Tue, 01 Mar 2005 14:06:57 +0200, Nikolaos Kavvadias
> <nkavv@p...> wrote:
> > -----BEGIN PGP SIGNED MESSAGE-----
> > Hash: SHA1
> >
> > Mike Delaney wrote:
> >
> > > Doh! I forgot that Xilinx gave out the source to the behavioral
> > > libraries for all the ASIC cells. Sorry about that.
> >
> > Please, could you refine on your statement? Any links to the Xilinx
> > stuff???
> 
> Well, the only way I know of (for free) is to download Xilinx Webpack
> and install it.  Look in the $XILINX/vhdl/src directory.  So you'll
> still need a Windows box, but the source is also included with the
> other (costly) versions of the Xilinx tools.  I'm not sure if they do
> have a seperate download for it or not.
> 
> >
> > > On Sat, 26 Feb 2005 14:53:12 -0500, Michael Hordijk
> > > <hoffbrinkle@h...> wrote:
> > >
> > >> <cut>
> > >>
> > >>> look at the manual, but it seems to suggest that using
> > >>> vendor-spefic parts, such as block RAMs, or ASIC multipliers or
> > >>> DSP blocks/slices,
> > >>
> > >> I've had no problems using the above simulator with any of the
> > >> Xilinx cores I use. Obviously, inferred parts are no problem.
> > >> It's compiled everything I need from unisim and XilinxCoreLib
> > >> with no problems. Supports VHDL 2002, etc.
> > >>
> > > _______________________________________________
> > > http://www.opencores.org/mailman/listinfo/cores
> > >
> > >
> > >
> >
> > -----BEGIN PGP SIGNATURE-----
> > Version: GnuPG v1.4.0 (MingW32)
> > Comment: Using GnuPG with Thunderbird - http://enigmail.mozdev.org
> >
> > iD8DBQFCJFrhMPiy0tCWlz4RApCaAKCdV9ZCpUG3PiIZyNfPwri5RCpXRQCeOx+V
> > uncMRLR4G3C54AZYU0+TcP0=
> > =XBHb
> > -----END PGP SIGNATURE-----
> >
> >
> > _______________________________________________
> > http://www.opencores.org/mailman/listinfo/cores
> >
> 
> ------------------------------
> 
> Message: 9
> Date: Tue, 1 Mar 2005 09:53:49 -0800
> From: "Sheila Carey" <sheilapcarey@d...>
> Subject: RE: [oc] Re: what opensource tools to use
> To: "'Mike Delaney'" <mmdst23@g...>,       "'Discussion list about free
>        open source IP cores'" <cores@o...>
> Message-ID: <20050301175353.4976.3932@h...>
> Content-Type: text/plain;       charset="US-ASCII"
> 
> And you'll find 16 Xilinx training sessions (free) here:
> 
> http://www.demosondemand.com/dod/proddemos/vendors/pd_xilinx.aspx
> 
> -----Original Message-----
> From: cores-bounces@o... [mailto:cores-bounces@o...] On
> Behalf Of Mike Delaney
> Sent: Tuesday, March 01, 2005 7:00 AM
> To: Discussion list about free open source IP cores
> Subject: Re: [oc] Re: what opensource tools to use
> 
> On Tue, 01 Mar 2005 14:06:57 +0200, Nikolaos Kavvadias
> <nkavv@p...> wrote:
> > -----BEGIN PGP SIGNED MESSAGE-----
> > Hash: SHA1
> >
> > Mike Delaney wrote:
> >
> > > Doh! I forgot that Xilinx gave out the source to the behavioral
> > > libraries for all the ASIC cells. Sorry about that.
> >
> > Please, could you refine on your statement? Any links to the Xilinx
> > stuff???
> 
> Well, the only way I know of (for free) is to download Xilinx Webpack and
> install it.  Look in the $XILINX/vhdl/src directory.  So you'll still need a
> Windows box, but the source is also included with the other (costly)
> versions of the Xilinx tools.  I'm not sure if they do have a seperate
> download for it or not.
> 
> >
> > > On Sat, 26 Feb 2005 14:53:12 -0500, Michael Hordijk
> > > <hoffbrinkle@h...> wrote:
> > >
> > >> <cut>
> > >>
> > >>> look at the manual, but it seems to suggest that using
> > >>> vendor-spefic parts, such as block RAMs, or ASIC multipliers or
> > >>> DSP blocks/slices,
> > >>
> > >> I've had no problems using the above simulator with any of the
> > >> Xilinx cores I use. Obviously, inferred parts are no problem.
> > >> It's compiled everything I need from unisim and XilinxCoreLib with
> > >> no problems. Supports VHDL 2002, etc.
> > >>
> > > _______________________________________________
> > > http://www.opencores.org/mailman/listinfo/cores
> > >
> > >
> > >
> >
> > -----BEGIN PGP SIGNATURE-----
> > Version: GnuPG v1.4.0 (MingW32)
> > Comment: Using GnuPG with Thunderbird - http://enigmail.mozdev.org
> >
> > iD8DBQFCJFrhMPiy0tCWlz4RApCaAKCdV9ZCpUG3PiIZyNfPwri5RCpXRQCeOx+V
> > uncMRLR4G3C54AZYU0+TcP0=
> > =XBHb
> > -----END PGP SIGNATURE-----
> >
> >
> > _______________________________________________
> > http://www.opencores.org/mailman/listinfo/cores
> >
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores
> 
> ------------------------------
> 
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> End of Cores Digest, Vol 16, Issue 1
> ************************************
>