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From: Guy Hutchison<ghutchis@g...>
Date: Wed Mar 2 19:16:27 CET 2005
Subject: [oc] a bit of newbie advice ..
On Wed, 2 Mar 2005 17:25:34 +0100, Lars Segerlund
<lars.segerlund@c...> wrote:
>
> Hi,
>
> I'm a bit new to verilog and I have the situation where I want to generate a clock
> from a clock available on the board, however the ratio is 3.5:1 i.e. I want a
> 8 MHz clock from a 28MHz clock source.
>
> Does anybody have any hint's or pointers in the right direction ?
>
> Right now I am thinking of adding a secondary clock source, but I would be glad if
> I could avoid it :-) .

One way you could tackle it is to use an on-chip PLL to multiply up
your clock source x2 (to 56 Mhz), then create a simple state machine
to divide by 7. If you're desiging with something that has built-in
PLLs and you're willing to live with a little jitter, it's cleaner
than trying to figure out how to create glitch-free combinatorial
logic.

- Guy