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-----Original Message-----

What do you mean when you say you don't get a response?
Can you check that your writing into the regs correctly (check CYC, STB).
The core should respond with an ACK.

Now if you're checking the scl and sda signals, make sure you hooked up the
tri-state output correctly and you pulled-up the wires.
Otherwise the core won't work.

Cheers,
Richard

> -----Original Message-----
> From: cores-bounces@o... 
> [mailto:cores-bounces@o...] On Behalf Of 
> David2565@h...
> Sent: Friday, January 21, 2005 4:34 PM
> To: cores@o...
> Subject: Re: [oc] I2C ip core integration for ALTERA FPGAs
> 
> Hi,
> 
> I tried to use this I2C core(the VHDL version) in a NIOS2 
> system with quartus 2(4.1) I connected everything like stated 
> below, but I get no response from it when I write to a register. 
> I did not connect the other end of the I2C chanel because I 
> want to make sure it was connected properly. Could that be 
> the problem?
> 
> I used the following commands to try to send something:
> [code]
> IOWR_8DIRECT(I2C_BASE,OC_I2C_CR,IORD_8DIRECT(I2C_BASE,
> OC_I2C_CR)|OC_I2C_EN); //chip enable
>  IOWR_8DIRECT(I2C_BASE,OC_I2C_PRER_LO,0x50);//set prescaler  
> IOWR_8DIRECT(I2C_BASE,OC_I2C_PRER_HI,0x00);
>  IOWR_8DIRECT(I2C_BASE,OC_I2C_TXR,0xAC);// set write adres  
> IOWR_8DIRECT(I2C_BASE,OC_I2C_SR,(IORD_8DIRECT
> (I2C_BASE,OC_I2C_SR)|OC_I2C_STA|OC_I2C_WR));//set some other 
> bits  printf("%x\n",IORD_8DIRECT(I2C_BASE,OC_I2C_SR));// check (i get
> FF!?)
>  while(IORD_8DIRECT(I2C_BASE,OC_I2C_SR)& OC_I2C_TIP);  
> printf("%x\n",IORD_8DIRECT(I2C_BASE,OC_I2C_SR));
>  IOWR_8DIRECT(I2C_BASE,OC_I2C_TXR,0x5C);
>  printf("%x\n",IORD_8DIRECT(I2C_BASE,OC_I2C_SR));
>  IOWR_8DIRECT(I2C_BASE,OC_I2C_SR,(IORD_8DIRECT
> (I2C_BASE,OC_I2C_SR)|OC_I2C_STO|OC_I2C_WR));
> [/code]
> 
> Hope someone can help,
> David
> 
> 
> ----- Original Message -----
> From: c.scherp@3...<c.scherp@3...>
> To: 
> Date: Thu Apr 15 16:20:50 CEST 2004
> Subject: [oc] I2C ip core integration for ALTERA FPGAs 
> 
> > Hallo Guido,
> > 
> > it works ! Thank you very much for helping me ! 
> > 
> > Christian. 
> > 
> > Datum: 	Fri, 2 Apr 2004 14:22:33 +0200 
> > Von: 	"Guido Kuhlmann" 
> > <Guido.Kuhlmann@t...> 
> > Betreff: 	RE: [oc] I2C ip core integration for 
> > ALTERA FPGAs 
> > An: 	"'Discussion list about free open source IP 
> > cores'" <cores@o...> 
> > Antwort an: 	Guido.Kuhlmann@t..., 
> >  	Discussion list about free open source IP cores <cores@o...> [ 
> > Doppelklick auf diese Zeile zeigt Optionen für Abo-Liste ] Hi 
> > Christian, you can easily connect the I2C Wishbone core to the NIOS 
> > processor (I don't know the simple I2C core).
> > 1. Within SOPC builder, generate interface to user logic. 
> > 2. Select bus interface type: avalon register slave. 
> > 3. Add "i2c_master_top.v" design file. 
> > 4. Read port list from file. 
> > 5. Connect the signals as follow: 
> >  wb_adr_i <=> address
> >  wb_dat_i <=> writedata
> >  wb_dat_o <=> readdata
> >  wb_we_i <=> write
> >  wb_stb_i <=> chipselect
> >  wb_cyc_i <=> chipselect
> >  wb_inta_o <=> irq
> >  wb_clk_i <=> clk
> >  wb_ack_o <=> waitrequest_n
> >  wb_rst_i <=> always0
> >  arst_i <=> reset_n
> >  scl_pad_i <=> export
> >  scl_pad_o <=> export
> >  scl_padoen_o <=> export
> >  sda_pad_i <=> export
> >  sda_pad_o <=> export
> >  sda_padoen_o <=> export
> > 6. Under timing tab, leave the setup, wait and hold settings at 0 
> > cycles.
> > You can now access the I2C core via included "oc_i2c_master.h".
> > Hope this helps. 
> > Guido. 
> > ______________________________________________________
> > _______
> >  Guido Kuhlmann
> >  Tigris Elektronik GmbH http://www.tigris.de 
> > ______________________________________________________
> > _______
> > > -----Original Message-----
> > > From: cores-bounces@o... 
> > > [mailto:cores-bounces@o...]On
> > > Behalf Of c.scherp@3... 
> > > Sent: Wednesday, March 31, 2004 10:31 AM
> > > To: cores@o... 
> > > Subject: [oc] I2C ip core integration for ALTERA FPGAs
> > > 
> > > 
> > > 
> > > I´m new to opencores.org and I want to integrate a simple
> > I2C
> > > Bus Master Interface
> > > in an ALTERA Apex / Cyclone / Stratix Device with 
> QuartusII and SOPC 
> > > Builder. I do not need the complex wishbone version of 
> the I2C core.
> > I´m
> > > happy with the simple
> > > I2C Bus Master which can be found in I2C.vhd. Is there any 
> > > documentation available for this version ? Or can anyone 
> give some 
> > > advice how to connect this core to the ALTERA Avalon Bus and the 
> > > ALTERA Nios Soft-Processor ? Thank
> > you... 
> > > Christian. 
> > > 
> > > 
> > > 
> > > _______________________________________________
> > > http://www.opencores.org/mailman/listinfo/cores
> > > 
> > _______________________________________________
> > http://www.opencores.org/mailman/listinfo/cores
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