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> 
> few doubts 
You're not having doubts, you're asking a question.

> regarding WISHBONE registered feedback cycle type. 
> WISHBONE master places a read command during first cycle.
> Is it necessary that master should accept the data during 
> second cycle ?
The master MUST accept the data when the master asserts CYC, STB, and the
slave asserts ACK.

> Can the master insert a wait state by deasserting strobe ?
IF the master negates STB, it will effectively insert wait states.
Note that the master probably shouldn't negate STB in the middle of a
transfer. It should do so at the start of a transfer.
For clearification, a transfer is defined as a single transfer of data
(stb->ack), a burst consists of multiple transfers.

> In that case will the slave come back with data during third cycle ?
> can anyone help..?
Could be yes. It all depends on the master and the slave.
Please read the spec and try to follow the examples.

Cheers,
Richard


> 
> Thanks in advance
> ambili
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