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Message
From: RT<mfoc73@d...>
Date: Tue Nov 2 10:25:57 CET 2004
Subject: [oc] XILINX easypath solutions
unmesh wrote:
> where I think XILINX saves money is that it needs to only do a functional
> test of the design with test vectors provided by the designer... so that
> board testing time which runs out to quite a lot if the complete fpga chip
> is to be tested. i think its a rather smart way to sell defective dies...
> one question..does anyone know of any tapeouts on easypath...just curious..
I don't know anything about Easypath, but I can't see that designers
would provide "test vectors". Most FPGA designers do limited
verification and couldn't produce the test vectors that would find
problems in the FPGA fabric. What's much more likely, as 'anon' says, is
that you provide a bitstream and Xilinx checks if it attempts to enable
a faulty part of the device. Xilinx saves money because it can recycle
faulty parts; it's nothing to do with reduced testing.
You can't "tape out" on an FPGA; you just program it. I'd be surprised
if Xilinx had many customers for this. The killer is that people buy
FPGAs because they can reprogram them, and you probably can't reprogram
an Easypath part. On the other hand, there is a (small) market for
one-shot FPGAs, so maybe they'll sell some parts.
I remember this used to be fairly common with DRAMs about 10 years ago -
you could buy cheap faulty parts, and the part number told you which
half of the device worked. The market went as yields went up.
thanks and regards
> Unmesh
>
> ----- Original Message -----
> From: <anon@a...>
> To: <cores@o...>
> Sent: Thursday, October 28, 2004 9:20 PM
> Subject: Re: [oc] XILINX easypath solutions
>
>
>
>>I don't have experience of Xilinx easypath, but I do have one or two
>>things to offer in response to your questions:
>>
>>Xilinx easypath is a service where Xilinx reduces its post-manufacture
>>test set to only cover the device's suitability for a particular
>>bitstream. So, when a product is ready to go to market, the customer
>>provides Xilinx with their bitstream and it is used to confidently
>>pass devices that would otherwise be failed.
>>
>>A trivial example: A design uses only 80% of the embedded multiplier
>>units in a Virtex II part. As long as the multipliers made use of are
>>operational who cares if the other multipliers are working? Note that
>>if the bitstream changes (e.g. bug correction) there is no guarantee
>>that it will work on easypath devices passed for the initial bitstream.
>>
>>It is interesting to note that over 90% of the programmability in the
>>routing fabric is effectively "don't care" for any single design.
>>Usually the device must be tested to ensure that all features are
>>working before it can be shipped to the customer.
>>
>>I would bet Xilinx only offers Easypath on the larger devices. This is
>>because manufacturing defects increase with the silicon area of the
>>device. The smaller devices will have close to 100% yield and there is
>>nothing to be gained from reducing the test set through easypath.
>>
>>----- Original Message -----
>>From: unmesh<unmesh@s...>
>>To:
>>Date: Thu Oct 28 06:52:46 CEST 2004
>>Subject: [oc] XILINX easypath solutions
>>
>>
>>>Hi All
>>> if wonder if anyone has any info on XILINX easypath solutions?
>>>have there been any design tape outs on easypath FPGAs.
>>> Thanks and regards
>>> Unmesh
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