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    Navigation: All forums > Cores > Message List > Message Post

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    From: Joachim Strömbergson<Joachim.Strombergson@I...>
    Date: Thu Oct 28 16:58:46 CEST 2004
    Subject: [oc] Small nitpick in the generic_dpram model
    Top
    Aloha!

    While browsing the code for the common RTL models in the CVS I found a small
    nitpick in the generic_dpram dual port memory model.

    the generic_dpram contains independent resets for the read and write port
    (rrst and wrst). But these are only used when the memory instanciated is
    defined as VENDOR_XILINX.

    It's quite clear that some other vendors don't have resets for their memories,
    but, IMHO, if a reset port is present, at least the generic model (i.e. the
    actual model, not a vendor instanciated memory) should use the resets. For
    starters they could be codified to behave like the Xilinx memory.

    Should I add code for it?

    --
    Med vänlig hälsning, Yours

    Joachim Strömbergson - Alltid i harmonisk svängning.
    VP, Research & Development
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