LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Sponsors
  • Mirrors
  • Logos
  • Contact us
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Navigation: All forums > Cores > Message List > Message Post

    Message

    Reply | Reply all
    Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

    From: unmesh<unmesh@s...>
    Date: Tue Oct 19 11:54:21 CEST 2004
    Subject: [oc] AHB Monitor.
    Top

    What environment are u developing? By monitor do u mean a protocol
    checker or a scoreboard? Also what's the RTL, an AHB master or an AHB slave
    and are u done developing the BFM?
    Regards

    ----- Original Message -----
    From: <ravindras.angadi@w...>
    To: <cores@o...>
    Sent: Tuesday, October 19, 2004 2:27 PM
    Subject: [oc] AHB Monitor.


    > Hi every body!
    >
    > I m designing a module for a AMBA-AHB "monitor" - can anybody plz
    > guide me how to go about it...
    >
    > The monitor should be capable for checking all the conditions of the
    > protocol.
    >
    > coding will be done in Verilog...
    >
    > I m new to this and expecting some help...
    >
    > thankyou
    > _______________________________________________
    > http://www.opencores.org/mailman/listinfo/cores

    Scanned by the SecureSynergy VirusScreen Service.
    For more information log on to : http://www.securesynergyonline.com or http://www.securesynergy.com

     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.