|
Message
From: Michael M Delaney
Date: Wed Oct 6 03:26:38 CEST 2004
Subject: [oc] DDR SDRAM controller Core
Has anyone used the DDR SDRAM controller core sucsusfully? I have it in a
block diagram with the mt46v16m16 memory model from Micron, and I will
either get a floating point exception from unisim, or a simulation for 100
ns will hang (ran for over 10 minutes on a P4 without responding).
I can't figure out what I'm doing wrong, or if it's in my block diagram,
or just in how I'm simulating it. I'm trying to do what's in the test
bench, except I'm using a mux to select between srd_clk and 0 as the
source for clk_fb, and I've never made it to doing the first write.
I'm using FPGA Advantage 6.2 with Modelsim SE Plus 5.7d, but I also have
no idea if the problem is with the tools, core, or the user.
Anyone have any suggestions?
Thanks,
Mike
|
 |
Browse
