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some related news..

This stuff is pretty cool.  It might be a good way to compile some DSP
programs into hardware in a seamless flow.

I haven't looked at it that closely, but I bet if we do, we'll find that
they aren't yet compiling C data structures into multiple memories, and
that many algorithms will be limited by memory access speeds.

Does anyone know if they support compilation of global arrays into
separate memories?  That might be enough for me to make use of.

Bill

On Wed, 2004-09-08 at 01:06, Ricky Nite wrote:
> some related news..
> 
> http://www.us.design-reuse.com/news/news8597.html
> 
> 
> Tensilica Announces Major IC Design Automation Breakthrough, The
> Automatic Generation of Optimized Programmable RTL Engines from
> Standard C Code 
> Automates RTL Block Design; Adds Flexibility through Programmability 
> 
> SANTA CLARA, Calif. - Sept. 6, 2004 - Tensilica(R), Inc. today
> announced that it has achieved a major design automation breakthrough
> - the automated design of optimized configurable processors from
> standard C code using the company's new XPRES (Xtensa(R) PRocessor
> Extension Synthesis) compiler. This tool enables the rapid development
> of optimized system-on-chip (SOC) devices without requiring designers
> to hand code their hardware using design languages like VHDL and
> Verilog, which take months of design and verification effort. 
> 
> Instead, designers input the original algorithm that they're trying to
> optimize, written in standard ANSI C/C++, and the XPRES compiler,
> coupled with Tensilica's automated processor generation technology,
> automatically generates an RTL (register transfer level) hardware
> description and associated software tool chain. In less than an hour,
> the resulting hardware block is delivered in the form of a
> pre-verified Xtensa LX processor core, enabling customers to future
> proof their designs due to its inherent programmability, and avoid the
> cost and risk associated with verifying custom logic. Additionally,
> the generated RTL fully rivals the performance and efficiency of
> hand-coded RTL blocks with many concurrent operations, efficient data
> types, and optimized multiple wide deep pipelines. 
> 
> http://www.us.design-reuse.com/news/news8597.html
> 
>  
> 
>  
> 
> 
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