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Message
From: Nikolaos Kavvadias<nkavv@s...>
Date: Wed Sep 8 18:35:10 CEST 2004
Subject: [oc] Winning with a reconfigurable computer
Well i have heard those Xtensa guys.You basically a 5-stage pipeline processor, and you get to write down the application-specific instructions running on specialized units. You write them in a kind of data-flow language (don't recall the name) and Verilog is generated. These units are placed at the execution (the 3rd) stage of the processor. I'm not aware if the processor template assumes pluging hardware accelerators interfaced through a bus (Wishbone, AMBA). In their publications, advanced instruction generation and selection algorithms have been presented. Mostly in papers of 2002 and after. Anyway, the mentioned article talks about behavioral synthesis, a hard issue. I'm not sure they have developed their technology or it is just a small step of the above execution unit synthesis. AFAIK behavioral synthesis results in 5x-10x less performance than hand-coding. I take examples of Celoxica and Confluence generated RTLs. Both techniques are impressive in the authenticity of approach, not performance (yet). What is a real possibility is to use "portable RTL". The traditional RTL approach, with records for input/output ports (now acceptable by common synthesis tools), let the synthesis tool decide the addition/multiplication hardware topology etc. This works within 10-15% of optimized coding for ASIC, but less for FPGA targets. regards Nikolaos Kavvadias
nkavv[at]skiathos.physics.auth.gr
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