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Message
From: Rudolf Usselmann<rudi@a...>
Date: Tue Sep 7 09:01:16 CEST 2004
Subject: [oc] Winning with a reconfigurable computer
On Tue, 2004-09-07 at 02:16, Bill Cox wrote:
[SNIP]
> The cache + traditional SRAM is a pretty good aproximation. However,
> there still seems to be only one data address bus in an Intel CPU. Data
> is inherently sequentially accessed. This can be improved upon.
I think this will be the biggest challenge. Problem is right
now that most CPUs implement multiple execution units which
can each use multiple data. Keeping them all fed will be tricky.
Even once the High Speed SRAM like memory will become available.
I suspect at some point all memories will be multi port, and
feature low pin count (multi) gigabit links to the CPU.
[SNIP]
> Cost is a real issue, as is trying to compete against Intel. However,
> having multiple memory systems working in parallel is potentially faster
> than the current single data bus architecture. So, for example, if
> every cycle the FPGA core receives all the data fields needed to execute
> a while loop, it could execute the whole thing in parallel. The Intel
> CPUs, on the other hand, still read just one memory data item per cycle,
> so far as I know.
Well, the only way you can do this right now is with address
guessing (aka prediction). And that will only marginal work.
EVERY CPU maker out there has tried to solve this problem and
I think all of them cam to the conclusion that it's impossible
to create a solution that is universal.
Sure as you say, if your memory can have unlimited port, you
will get much closer to the solution, but cost is a factor ...
> It's always good talking to you.
>
> Bill
Anyway, allow me to redirect this whole discussion to a slightly
different direction. I actually think this is what you really
want to do: Problem Specific CPUs.
Going against Intel and trying to compete with them, is really
a tough job. Unlike Microsoft, I believe Intel has actually
quite a few very bright engineers and I have a lot of respect
for what they have accomplished, same goes for AMD.
Here are two bad examples of problem specific CPUs (lets call
them PSCPUs):
- Java Processor
- Verilog Processor (I know a company was developing this at
one point, but don't know if it ever became a product or not).
The reason I call these bad examples, is because they are still
trying to solve generic problems, by using difference languages
and representations.m.
Two years ago I worked on PSCPU with a British company. The
project fell through for various other reasons. The idea was
to build an accelerator for Spice/HSpice simulator. One guy
who was a mathematician, sat down and plugged the spice code
apart, and decided that all he needed to accelerate the inner
loop was a massive parallel matrix multiplier. So we where
going to build just that. It would include some sort of sequencer
and data steering, and the heart of it would be a matrix
multiplier. We would use an array of these units interconnected
to each other and some memory to solve a dedicated problems.
This is just an example of where I am trying to go. Perhaps
what you, Bill, really want is a dedicated engine that can
accelerate routing, or solve some other sort of *dedicated*
problem ? Thats something I think we can do at OpenCores.
Competing with Intel on the other hand, I would seriously
doubt !
Regards,
rudi
=============================================================
Rudolf Usselmann, ASICS World Services, http://www.asics.ws
Your Partner for IP Cores, Design, Verification and Synthesis
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