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Message
From: Guy Hutchison<ghutchis@g...>
Date: Sat May 15 08:17:46 CEST 2004
Subject: [oc] Quick Start on Opensource ASIC design VLSI Tools
> That essentially IS logic sysnthesis of standard VHDL RTL
> aftet this you get a VHDL gatelevel netlist made up with
> standrad cells from the library sxlib ( sxlib is distributed with Allance)
Unforunately, neither Verilog nor VHDL has ever defined what portion
of the language constitutes the synthesizable subset, and so we are
left with de facto standards. The bar for this is whatever VHDL code
can be accepted by common synthesis tools as Design Compiler and
Get2Chip. While VASY does support more constructs than I thought it
did, it was unable to translate several VHDL files (from
opencores.org) which I have previously compiled with DC.
This means that, in practice, unless you are coding specifically for
the Alliance tool set, compiling your code with VASY will require
rewriting substantial portions of it.
My comment about being misleading was that if you make a statement
like "tool XXX supports logic synthesis" with no conditions or
caveats, anyone looking at the tool will expect it to have roughly the
same capabilities and limitations of other tools that support logic
synthesis; VASY/BOOM does not meet these criteria.
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