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From here OCP (placer for Standar Cells) and OCR (over the Cell router)

Thats true that Alliance implements a subset of VHDL 
BUT
Theres a front end tools called VASY with it that can take
 RTL VHDL and change it to the Allaince VHDL subset

The tool BOOG (Binding and Optimization on Gates) IS
 essentially a logic sysnthesis tool for the Allaince subset
 of VHDL.

So when you do VASY->BOOM->BOOG->LOON
(BOOM - Bolean Minimization )
(BOOG - Binding and Optimization)
(LOON - Local Optimization on nets)

That essentially IS logic sysnthesis of standard VHDL RTL
aftet this you get a VHDL gatelevel netlist made up with
 standrad cells from the library sxlib ( sxlib is distributed with Allance)

>From here OCP (placer for Standar Cells) and OCR (over the Cell router)
 or Nero (Negotinting Router) can be used for place and route

so my statement was not 'highly misleading' 

----- Original Message ----- 
From: "Guy Hutchison" <ghutchis@g...>
To: "Discussion list about free open source IP cores" <cores@o...>
Sent: Friday, May 14, 2004 7:12 AM
Subject: Re: [oc] Quick Start on Opensource ASIC design VLSI Tools

> > among others Logic Synthesis and place & route tools for standard 
> 
> I've played around some with the Alliance tool set, and this statement
> is highly misleading.  While there are two tools which are called
> "logic synthesis", they would not be recognized as a synthesis tool by
> most FPGA/ASIC designers.
> 
> The Alliance tools can tackle only a very small subset of VHDL, whose
> level of abstraction is roughly that of a gate level description. 
> Unless something has changed since when I last looked at the tools,
> they would not be able to synthesize any of the designs found on
> OpenCores.
> 
> The back-end tools are much more complete, although I don't believe
> that they are timing-aware.
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores