|
Message
From: Guy Hutchison<ghutchis@g...>
Date: Fri May 14 08:12:29 CEST 2004
Subject: [oc] Quick Start on Opensource ASIC design VLSI Tools
> among others Logic Synthesis and place & route tools for standard
I've played around some with the Alliance tool set, and this statement
is highly misleading. While there are two tools which are called
"logic synthesis", they would not be recognized as a synthesis tool by
most FPGA/ASIC designers.
The Alliance tools can tackle only a very small subset of VHDL, whose
level of abstraction is roughly that of a gate level description.
Unless something has changed since when I last looked at the tools,
they would not be able to synthesize any of the designs found on
OpenCores.
The back-end tools are much more complete, although I don't believe
that they are timing-aware.
|
 |
Browse
