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Message
From: Bill Cox<bill@v...>
Date: Wed May 12 23:44:42 CEST 2004
Subject: [oc] One issue about free hardware
On Wed, 2004-05-12 at 15:42, Richard Stallman wrote:
> So
> in my previous post, when I say "open-source", I really mean "free
> software". Your comments would be appreciated.
>
> Ok.
Just my two cents on terminology... An old evil marketing trick is to
subvert other's terms and causes. It can work both ways... If people
want to call their free software "open source", why fight them. It
might be easier to encourage the use of "open source" to mean "free
software" in casual use (as seems to be happening). That way, the evil
marketing guys don't really have a slick term any more to describe
non-free software in a positive way.
The letter i means the imaginary number to a mathematician, but current
to an engineer, who uses j for the imaginary number. The term IP to an
engineer means hardware cores. To a lawyer it means just about any
non-physical thing other than money that can be owned. The term AI to
an MIT grad usually means artificial intelligence. To a horse breeder,
it's got a much different meaning. I think there's no danger of people
on this forum getting confused by the term IP.
>
> The bigger problem is the complete lack of an free-software flow from=20
> RTL to implementation. There is simply no GCC equivalent for=20
> compiling digital logic -- every ASIC and FPGA designer is at the=20
> mercy of [non-free] tools on the font-end. (My biggest pet-peeve is=20
> FPGA synthesis. FPGAs have had dual-port RAMs for ~7 years now, yet=20
> we still can't infer dual-port block RAM from HDL. Arggh!)
>
> One hurdle to free-software synthesis and place&route is proprietary=20
> architectures. The major FPGA vendors refuse to disclose the=20
> underlying details needed to for a quality PAR tool or physical=20
> synthesis.
>
> Can people figure that out by studying some FPGAs' design structure,
> or does it change so often that it would be useless?
It can and has been done, but it's not easy. From a practical point of
view, this is just one of the hard tasks involved. I work on a
structured ASIC place and route toolkit that has similar complexity to
FPGA place and route. There's about 500K lines of C code in our system
now. I'll be Xilinx has millions.
> But oddly enough the biggest roadblock to free-software EDA is=20
> ourselves. For some reason or another, there is an apparent lack of=20
> interest and motivation. Just a few examples:
>
> 1. Every couple of months the topic of free-software tools arise. =20
> Generates quite a bit of discussion, then dies as quickly as it=20
> started.
>
> It always takes more than just superficial interest to get something
> to work.
This is the core problem. We'd need a bunch of guys with a LOT of free
time and strong interest to pull this off. Here's a datapoint to
consider:
A highly respected Ph.D. grad from the University of Toronto wrote what
was probably the best open-source FPGA place and route toolkit available
at the time (VPR). There are only 32K lines of C code. The tool might
be a good starting point, but it's just that.
> 2. With Confluence under GPL, I have yet to receive a single bug=20
> report or source code contribution.
>
> What is Confluence, and what does it do?
>
> (I can't see access a web page except by sending mail, and I would not
> get the page contents it until the next batch of mail.)
Did you try www.launchbird.com?
In a nutshell, confluence is a module generation language. It fits a
big hole that currently exists in the EDA design flow. For example, if
I want to write code in Verilog to generate optimized adders depending
on bit width, speed, and requirements, I'm out of luck. I think this
ability was added to SystemVerilog. It's possible to do in VHDL, but
VERY ugly. Confluence is written in O'caml, and is a fairly simple,
powerful, and elegant language for specifying algorithms used to
construct complex parameterized components.
> 3. Icarus Verilog, the foremost free-software Verilog implementation,=20
> still only has one active developer.
>
> The FSF could put that on our list of projects to recommend people
> contribute to. Would the developer of it like to contact me?
> (If you know how to contact him, could you ask him to?)
IMO, this is the single most impressive EDA open-source project out
there. He (Stephen Williams -- steve-at-NOSPAMicarus_dot_com) monitors
the gEDA list at www.geda.seul.org. I'll post a message asking him to
contact you.
> 4. The only semi-successful FPGA packing, placement, and routing=20
> project haulted activity in March, 2000.
>
> What stopped it?
I'd be interested in knowing which effort this was. I think it probably
halted because it's a really big task. Not as big as re-writing UNIX,
but most of us think a bit smaller...
> 5. The one person who came the closest to reverse engineering the=20
> Virtex bit stream -- the critical step for physical synthesis --=20
> became frustrated with the lack of support and interest from the FPGA=20
> community, and finally closed shop on 12/24/2003.
>
> What kind of support did he need? Also, who does "FPGA community"
> refer to in this context? (I see multiple possibilities.)
>
> Depending on what he needs, maybe the FSF could provide it,
> if you can put me in touch with him.
Can't help you here. I didn't know there was an ongoing effort. I'd
like to know which forums he was posting to.
Bill
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