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Message
From: awciesla at uiuc.edu<awciesla@u...>
Date: Tue Apr 20 06:46:21 CEST 2004
Subject: [oc] random integer - VHDL
hello, ive been searching around awhile now to no avail. I'm looking for
some way in vhdl to generate a random integer or sequence. It doesnt
have to be anything fancy at all, just some way to even generate a
pseudo random integer would work. i would appreciate any help or
suggestions, thanks!
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