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-----Original Message-----

CYC is asserted during the transfer of 1 or more data.
STB is asserted during the transfer of 1 datum.

So a single assertion of CYC can contain multiple assertions of STB.

A core should only respond to (other) wishbone signals when CYC is asserted.

A transfer is valid when cyc & stb & ack are asserted.

Cheers,
Richard

> -----Original Message-----
> From: cores-bounces@o... [mailto:cores-bounces@o...] On
> Behalf Of Martin.J Thompson
> Sent: Monday, March 29, 2004 10:36 AM
> To: <
> Subject: [oc] Wishbone Spec - use of CYC signal
> 
> Hi all,
> 
> We've been poring over the Wisbone spec (revision B3) and are confused by
> the Examples in the appendix...
>   RULE 3.30 states that slaves should only respond to inputs when CYC is
> asserted.
> 
> The examples in Appendix 6 don't show the use of CYC to qualify anything -
> are they therefore non-wishbone compliant?  I ask because our processor to
> WB bridge generates STBs for every processor access to its external bus
> (whetehr or not they are targetted at us) and I'm worried that if the open
> cores blocks have been designed with the A6 examples rather than to the
> spec they will fail as they will see lots of strobes which they should be
> ignoring, but won't!
> 
> Thanks,
> Martin
> 
> --
> Martin Thompson CEng MIEE
> TRW Conekt
> Stratford Road, Solihull, B90 4GW. UK
> Tel: +44 (0)121-627-3569 - martin.j.thompson@t...
> 
> 
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