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Message
From: Bill Cox<bill@v...>
Date: Fri Feb 6 16:41:22 CET 2004
Subject: [oc] Off-topic: about ASIC manufacturing
Hi, Steven.This line of discussion sounds dangerously like an add for my companies
products, so please just skip it, unless you really feel like reading
more nonsense about structured ASICs. However, in the end, I'm not a
nuetral party. I'm a structured ASIC fanatic.
Redant Steven wrote:
>Dear Bill,
>
>
>
>>These services are wonderful. The chip they make are great for
>>prototypes, but too expensive for production. I checked the published
>>prices on the Mosis web site, and for their most advanced silicon, it
>>comes out to over $1,000 US dollars per part, and the part is untested.
>>
>>
>
>That depends on how many chips you want. You can go for small volumes (definition being: any volume the foundry doesn't want to give to you) too.
>This can be up to a million pieces of a rather small chip e.g.
>
>Hence there are some extra questions:
>What technology have you calculated with? How many parts? Only a protoype run that gives you a very limited amount of parts?
>
I want to make parts available all the way down the most advanced
process available (about 90nm today). I'd like to ship quantities in
multiples of about 5,000 parts. Here's some simple math that does the
trick for me:
Wafer runs in .13u of 50 8" wafers cost about $150K. The masks cost
about $750K. Obviously, a Mosis style multi-project wafer product can
never be cost-effective.
The same runs of wafers using only one custom via-mask has less than
$40K worth of custom masks. The wafer costs dominate. Thus, we can
produce cost effective products in very low or very high volume this
way. Also, our logic + SRAM fabric is slightly denser than gate arrays
+ SRAM, so our die are very small and cost effective. Doing the math
for a 4mm^2 die, our wafer cost + NRE per spot on a multi-project
retical turn out to be about $2K. Selling you 5K parts of .13u for less
than $15K sounds totally doable.
>>I think for the average guy out there who just whats to make a million
>>dollars, ASICs are no longer affordable. I want to change that.
>>
>>
>
>Well, that depends. It's not necessary to use the most advanced technologies to make an application that will make you a million bucks. If you stay in the 'bigger' technologies ASICS are very affordable still. If you want to use e.g. .13 it's another story.
>
>Testing setup (SW/HW) cost is also amortized over the amount of chips you want to make.
>
>I would be very pleased to hear about novel ideas to get the cost of ASICs down for smaller volumes!
>
In .35u vs the 90nm FPGAs that are being designed now, the ratio of
transistors/unit silicon is 15. The difference in silicon area in the
same process of standard-cell vs FPGA logic fabric is somewhere around
50x. The difference of between a .35u ASIC and a 90nm FPGA is now only
a ratio of 3.3.
I hate to be the bringer of bad news, but ASICs as we know them are
going away. However, the emerging market of structured ASICs can help
fill the void.
Again, my opinions in this area are highly biased. I own a fair chunk
of Synplicity stock (who seems to be doing well in structured ASICs),
and a big chunk of ViASIC stock, and we write software that enables this
stuff. However, the reasons I'm invested this way are that the writing
on the wall for ASICs is clear.
Bill
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