LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Advertise
  • Mirrors
  • Logos
  • Contact us
  • Find Resources
  • Job Opportunity
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Navigation: All forums > Cores > Message List > Message Post

    Message

    Reply | Reply all
    Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

    From: sunyzs@1...
    Date: Thu, 14 Aug 2003 04:43:58 +0200
    Subject: [oc] vhdl about hdbn module?
    Top

    1.could you explain the InsertBBit process?
        InsertBBit: process (Reset_i, Clk_i)
        begin
            if Reset_i = '1' then
                Q5 <= '0';
            elsif rising_edge(Clk_i) then
                if ClkEnable_i = '1' then
                    Q5 <= Q4 or (ZeroString and (not ViolationType));
                end if;
            end if;
        end process InsertBBit;
    2.what's the meaning of ViolationType?
    thx.
    
    
    
     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.