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    Navigation: All forums > Cores > Message List > Message Post

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    From: Lars Segerlund <lars.segerlund@c...>
    Date: Wed, 13 Aug 2003 13:11:17 +0200
    Subject: Re: [oc] pseudo random generator verilog code source
    Top

    
      If you got some ram to spare you might want to check out the Mersenne 
    twister pseudo random generator, since it's got really good metrics, 
    otherwise you might want to try 'ent' a little program to calculate the 
    entropy of the generated sequence in order to some extent verify the 
    quality of the implementation.
    
      / regards, Lars Segerlund.
    
    ni_zhihong@s... wrote:
    > ----- Original Message ----- 
    > From: Victor Snesarev <vnsnes@y... > 
    > To: cores@o...  
    > Date: Thu, 19 Sep 2002 12:14:25 -0700 (PDT) 
    > Subject: Re: [oc] pseudo random generator verilog code source 
    > 
    > 
    >>
    >>I wrote up a webpage about using LSFRs (Linear Shift 
    >>Feedback Registers) for pseudo-random number 
    >>generation during time off work, maybe it will help: 
    >>
    >>http://vnsnes.freeshell.org/lfsr/index.shtml 
    >>
    >>A link to an old Altera LFSR core is at the bottom of 
    >>the page. 
    >>
    >>Hope this helps. 
    >>
    >>--- olupas@o...  wrote: 
    >>
    >>>Hi all, 
    >>>
    >>>This will generate only one new bit per clock. 
    >>>Maybe you need 32 new bits per clock, to send 
    >>>over a network ... 
    >>>
    >>>A good starting point might be AN49 from Altera. 
    >>>
    >>>I was unable to find this on the web, so I have 
    >>>built my owns, 
    >>>starting from there. 
    >>>
    >>>Unfortunately,  I cannot send the sources 
    >>>but I can help you with hints. 
    >>>
    >>>Cheers, 
    >>>Ovidiu Lupas. 
    >>>
    >>>
    >>>
    >>>----- Original Message ----- 
    >>>From: Marko Mlinar <markom@o... > 
    >>>To: cores@o... 
    >>>Date: Thu, 19 Sep 2002 10:55:46 +0200 
    >>>Subject: Re: [oc] pseudo random generator verilog 
    >>>code source 
    >>>
    >>>
    >>>>
    >>>>Here: 
    >>>>
    >>>>reg [31:0] poly; 
    >>>>
    >>>>always @(posedge clk or posedge reset_poly) 
    >>>>  if (reset_poly) poly <= #1 32'hdeaddead; 
    >>>>  else poly <= #1 {poly[30:0], poly[17] ^ 
    >>>
    >>>poly[4]}; 
    >>>
    >>>>On Thursday 19 September 2002 09:54, Dharmeshbhai 
    >>>
    >>>PATEL wrote: 
    >>>
    >>>>>Hi list, 
    >>>>>
    >>>>>Does any one has an idea where i can get the 
    >>>
    >>>verilog code 
    >>>
    >>>>source 
    >>>>
    >>>>>for a pseudo random generator (number or signal) 
    >>>
    >>>? 
    >>>
    >>>>>Please let me know. 
    >>>>>
    >>>>>Thanks in advance. 
    >>>>>D.PATEL 
    >>>>>
    >>>>>
    >>>>>
    >>>
    > _____________________________________________________________
    >  
    > 
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    >>>
    >>>>de Wanadoo ! 
    >>>>
    >>>>>Vivez l'Internet sans contrainte en bénéficiant 
    >>>
    >>>d'un prix 
    >>>
    >>>>"tout compris", 
    >>>>
    >>>>>d'un forfait haut débit illimit? d'un accès 
    >>>
    >>>ADSL et d'un 
    >>>
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    >>>>
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    >>>>
    >>>
    > 
    > 
    
    
    
    

    ReferenceAuthor
    Re: [oc] pseudo random generator verilog code sourceNi_zhihong

     
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