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Message
From: Shehryar Shaheen <shehryar.shaheen@u...>
Date: Fri, 30 May 2003 17:17:12 +0100
Subject: Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
----- Original Message -----
From: "Shehryar Shaheen" <shehryar.shaheen@u...>
To: <cores@o...>
Sent: Friday, May 30, 2003 5:10 PM
Subject: Re: [oc] Verilog coding style for Open Cores-RTL - Case in point
SHA1
>
> ----- Original Message -----
> From: "John Sheahan" <jrsheahan@o...>
> To: <cores@o...>
> Sent: Thursday, May 29, 2003 11:38 PM
> Subject: Re: [oc] Verilog coding style for Open Cores-RTL - Case in point
> SHA1
>
>
> > On Thu, May 29, 2003 at 10:26:48PM +0100, Shehryar Shaheen wrote:
> > >
> > > > Is there any quickly way to code a netlist given a
> > > > handful of components without having to worry about execution order?
> > >
> > > All declared concurent processes will execute in parallel much like
all
> > > always blocks
> > > in verilog execute in parallel and all processes in VHDL.
> >
> > you appear to have ducked this question. Instantiations and assigns
> > are parallel too, and are short and clear.
>
> Modules can be instatiated in SystemC.
> Like the xyz module can be instatited like
>
> xyz xyz_inst("xyz_1");
> xyx_inst.clock( -- signal to connect to--);
> xyz_inst.din1 (-- signal to connect to --);
> xyz_inst.din2 (-- signal to connect to --);
> xyz_inst.dout1(-- signal to connect to --);
> xyz_inst.dout2(-- signal to connect to --);
>
> For SystemC equivalent of assign
>
> first a simple verilog module with an assign
>
> module abc(
> din1
> ,din2
> ,sel
> ,dout1);
>
> input din1;
> input din2;
> output dout1;
>
> assign dout1 = sel ? din1 : din2;
> endmodule
>
> In SystemC
>
> SC_MODULE(abc)
> {
> sc_in<bool> din1;
> sc_in<bool> din2;
sc_in<bool> sel;
> sc_out<bool> dout1;
> void func()
> {
> dout1 = sel ? din1 : din2;
> };
> SC_CTOR(abc)
> {
> SC_METHOD(func);
> sensitive << din1 << din2 << sel;
> }
> };
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