OPENCORES.ORG

From: John Sheahan <jrsheahan@o...>
Date: Fri, 30 May 2003 08:38:32 +1000
Subject: Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1

On Thu, May 29, 2003 at 10:26:48PM +0100, Shehryar Shaheen wrote:
> 
> > Is there any quickly way to code a netlist given a
> > handful of components without having to worry about execution order?
> 
> All declared concurent processes will execute in parallel much like all
> always blocks
>  in verilog execute in parallel and all processes in VHDL.

you appear to have ducked this question. Instantiations and assigns 
are parallel too, and are short and clear.
john

Reference Author

Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1 Marco Antonio Simon Dal Poz

Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1 Marko Mlinar

Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1 Shehryar Shaheen

Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1 Tom Hawkins

Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1 Shehryar Shaheen

Follow up Author

Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1 Shehryar Shaheen