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    Navigation: All forums > Cores > Message List > Message Post

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    From: Tom Hawkins <tom1@l...>
    Date: Thu, 29 May 2003 13:59:53 -0500
    Subject: Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
    Top

    On Thursday 29 May 2003 10:51 am, Shehryar Shaheen wrote:
    > To say SystemC is not a Concurent but a Sequential
    >  language is a misleading statement and is perhaps bad
    >  understanding of SystemC.
    >
    > Most simulators are single kernel simulators but in SystemC the
    >  kernel is built into the executable binary which gives the
    >  concurency similar to the verilog 'always' or the VHDL 'process'
    > block.
    >
    > A  sample verilog module with two always block like.....
    >
    > module xyz(din1,din2, clock, dout1,dout2);
    > input din1;
    > input din2;
    > input clock;
    > output dout1;
    > output dout2;
    >
    > reg dout1;
    > reg dout2;
    >
    > always @(posedge clock)
    > dout1 <= din1;
    > always @(posedge clock)
    > dout2 <= din2;
    >
    > endmodule
    >
    > ......... would look like the following in SystemC
    >
    > SC_MODULE(xyz)
    > {
    > sc_in<bool> din1;
    > sc_in<bool> din2;
    > sc_in<bool> clock;
    > sc_out<bool> dout1;
    > sc_out<bool> dout2;
    > void func1()
    > {
    > dout1 = din2;
    > };
    > void func2()
    > {
    > dout2 = din2;
    > };
    >
    > SC_CTOR(xyz)
    > {
    > SC_METHOD(func1);    <-----+
    > sensitive_pos << clock;              |---- Both these functions
    > will now execute concurently when this module is instantiated
    > SC_METHOD(func2);    <-----+
    > sensitive_pos << clock;
    > }
    > };
    >
    > This is just an example with no useful logic implemented in the
    > modules but its just to show that functions registed as
    >  SC_METHOD in the constructor (SC_CTOR) are equivalent to the
    > Verilog always or VHDL process blocks
    
    I don't know SystemC, but it appears parallelism is only explicit, 
    i.e., you have go through an API to declare concurrent processes.  Is 
    this true?  Is there any quickly way to code a netlist given a 
    handful of components without having to worry about execution order?  
    This is probably the main reason RTL designers prefer their HDL.
    
    Line counts for xyz:
      SystemC = 23 lines
      Verilog = 13 lines
      Confluence = 5 lines:
    
    Xyz <-
      comp +Din1 +Din2 -Dout1 -Dout2
        {Reg, 1 Din, Dout}
        {Reg, 1 Din, Dout}
      end
    
     
    
    -- 
    Tom Hawkins
    Launchbird Design Systems, Inc.
    952-200-3790
    tom1@l...
    http://www.launchbird.com/
    
    
    
    
    

    ReferenceAuthor
    Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1Marco Antonio Simon Dal Poz
    Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1Marko Mlinar
    Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1Shehryar Shaheen

    Follow upAuthor
    Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1Shehryar Shaheen

     
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