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Message
From: =?ISO-8859-15?B?SOljdG9yIE9y824gTWFydO1uZXo=?= <hecormar@t...>
Date: Mon, 26 May 2003 13:06:51 +0200
Subject: [oc] VHDL Help...
Dear cores,
Well, my problem is that writing an entity i have to use two
variables, but i think it is a way to write it with one variable,
i don't know if this line is correct, but compiler tells me it
isn't... do you think that i could do it this way ?
PROBLEM ON: (ceil(log2(tamany_data)))
--< CODE > ---------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY mux IS
GENERIC( size_data : integer := 8 );
PORT(
data : IN STD_LOGIC_VECTOR(size_data-1 downto 0);
** sel : IN STD_LOGIC_VECTOR(ceil(log2(size_data)) downto 0); **
result : OUT STD_LOGIC
);
END mux;
--< END CODE >----------------------------------------------------
--
Cheers,
Héctor mailto:hecormar@o...
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