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Message
From: Tom Hawkins <tom1@l...>
Date: Thu, 22 May 2003 09:34:34 -0500
Subject: Re: [oc] Verilog vs VHDL vs Other
On Thursday 22 May 2003 01:39 am, Marko Mlinar wrote:
>
> Tom,
>
> first thanks for your contribution. I am sure Confluence can be
> handy in certain cases, e.g. DSP processing, like you already
> mentioned on your web site.
>
> I will try to give you some (much wanted, I suppose) feedback:
> Although you would probably say Confluence is a complete language
> unfortunately it does not solve all the todays problems, especially
> with integration and configuration.
Confluence doesn't solve all todays problems. But it certainly works
well for constructing and validating pure synchronous RTL, which
probably accounts for 90% of all logic design. I would like to hear
your concerns with integration and configurations. Confluence
designs are far more configurable than HDL, because every Confluence
variable is a "configuration parameter".
> It is also functional language, and this programming paradigm is
> rather new to both SW and HW people. Who has wrote an application
> in Huskell, for example?
Very true. Ironically, HW designers adapted quicker to functional
programming (FP) that SW people. FP is nothing more that
instantiating and wiring components (aka. functions) together -- a
concept every RTL designer practices everyday.
Our biggest concern would be how HW designers take to recursive and
first class components. The early Confluence evaluators have shown
that these concepts are not a problem.
In fact, we had an FPGA design consultant download the tools on a
Friday, spent the weekend learning the language, and by Monday had
already finished a large design component he had previously told his
customer would take another week to complete. It wasn't a trivial
project either; it involved filtering and color-factor correction of
4M pixel camera images.
This comes from a guy who has never used an FP language before in his
life. But because he has a solid RTL background, his transition to
Confluence was easy.
> It also has strange grammar, which is
> neither similar to C neither to Verilog/VHDL, so first impression
> gives an impression of rather obscure language, although it is very
> well defined.
Like any language, the grammar does look a little weird at first. We
specifically designed the syntax for instantiating and wiring
components. Once you understand how components are defined and
instantiated, and have a grasp of a handful of operators, the syntax
becomes clear. Every time I give a demo, the syntax learning curve
is usually only 5 minutes.
>
> best regards,
> Marko
Thanks for your input!
Regards,
Tom
--
Tom Hawkins
Launchbird Design Systems, Inc.
952-200-3790
tom1@l...
http://www.launchbird.com/
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