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From: "Sridhar" <nandulasridhar@i...>
Date: Thu, 22 May 2003 13:44:36 +0530
Subject: Re: [oc] a question about Verilog coding ...

As far as I know, it cannot. where as in VHDL operator overloading is possible. we can say this is one limitation in verilog. 

Regards,
Sridhar
Team leader
Wireless Design group
nandulasridhar@y...

cores@o... wrote:
Hi friend£¡

   whether the verilog can overload a operater ? if can ,how?
			
Best Regard
 
				 
¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡henry_xb
¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡xxiaobin@2...
¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡2003-05-22







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