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From: Marko Mlinar <markom@o...>
Date: Thu, 22 May 2003 08:39:23 +0200
Subject: Re: [oc] Verilog vs VHDL vs Other

On Wednesday 21 May 2003 17:38, Tom Hawkins wrote:
> The V versus V debate has gone on ever since the birth of HDL and it
> will continue to a "topic of discussion" (putting it mildly) for
> years to come.  Both languages have their strengths, but both are
> also fundementally flawed.
>
> Some evidence of this are the countless Perl scripts used to
> manipulate and manage HDL code -- practically every design house has
> a suite of custom tools for this purpose.  There are several other
> language extensions built to either aid in RTL construction or assist
> in modeling.  A short list includes:
>
> ParaCore - http://www.dilloneng.com/paracore.shtml
> RubyHDL - http://www.aracnet.com/~ptkwt/ruby_stuff/RHDL/index.shtml
> MyHDL - http://jandecaluwe.com/Tools/MyHDL/Overview.shtml
> JHDL - http://www.jhdl.org/
> Lava - http://www.xilinx.com/labs/lava/
> HDLmaker - http://www.polybus.com/hdlmaker/users_guide/
>
> The main purpose of a language -- programing, hdl, or otherwise -- is
> to ease the expression of design.  If either Verilog or VHDL were
> adequate, most of these hacks would not be necessary.
>
> It's not the fault of either.  Both languages are 20 years old.  20
> years ago, they were excellent modeling languages.  Then 15 years
> ago, Synopsys Design Compiler came along and made them excellent
> design languages.  But today, Verilog and VHDL are having a hard time
> keeping up with Moore's law.

> I would like to donate Confluence to the OpenCore community.  Maybe
> have the tools on the server side, so anyone could generate Verilog,
> VHDL, and C from any Confluence open core.  Any ideas?

Tom, 

first thanks for your contribution. I am sure Confluence can be handy in 
certain cases, e.g. DSP processing, like you already mentioned on your web 
site.

I will try to give you some (much wanted, I suppose) feedback:
Although you would probably say Confluence is a complete language 
unfortunately it does not solve all the todays problems, especially with 
integration and configuration.
It is also functional language, and this programming paradigm is rather new to 
both SW and HW people. Who has wrote an application in Huskell, for example?
It also has strange grammar, which is neither similar to C neither to 
Verilog/VHDL, so first impression gives an impression of rather obscure 
language, although it is very well defined.

best regards,
Marko

Reference Author

Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1 Marco Antonio Simon Dal Poz

Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1 Joachim

[oc] Verilog vs VHDL vs Other Tom Hawkins

Follow up Author

Re: [oc] Verilog vs VHDL vs Other Tom Hawkins